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11. 发明公开

EP2587545A1 High-voltage vertical FET and method of manufacturing the same 审中-公开
标题翻译： Vertikaler Hochspannung-FET和Verfahren zu dessen Herstellung
公开(公告)号：EP2587545A1
公开(公告)日：2013-05-01
申请号：EP13152055.3
申请日：2007-11-28
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay
IPC分类号： H01L29/78 , H01L29/423 , H01L29/40 , H01L29/06 , H01L21/77
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： A transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.
摘要翻译：制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。在一行或一列中的相邻部分定向成使得第一相邻部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。

12. 发明公开

EP2549540A3 High-voltage vertical FET 审中-公开
标题翻译：高压垂直FET
公开(公告)号：EP2549540A3
公开(公告)日：2013-02-20
申请号：EP12180878.6
申请日：2007-09-04
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Grabowski, Wayne, Bryan
IPC分类号： H01L29/78 , H01L29/40 , H01L29/06 , H01L21/77 , H01L29/423
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在半导体管芯的与第一区域相邻的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二介电区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二介电区域中。邻接第一和第二部分的晶体管部分的外部场板或者是分开的或者是部分合并的。

13. 发明公开

EP2482325A2 Deep trench insulated gate bipolar transistor 审中-公开
标题翻译：栅双极型晶体管tiefgrabenisoliertem
公开(公告)号：EP2482325A2
公开(公告)日：2012-08-01
申请号：EP12165169.9
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/0649 , H01L29/0653 , H01L29/66348
摘要： In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second conductivity type that adjoins a top surface of the buffer layer, and a body region of the first conductivity type. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.

14. 发明公开

EP2482321A2 Method of fabricating a deep trench insulated gate bipolar transistor 审中-公开
标题翻译：一种用于生产具有栅极tiefgrabenisoliertem双极晶体管过程
公开(公告)号：EP2482321A2
公开(公告)日：2012-08-01
申请号：EP12164827.3
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L21/331 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

15. 发明公开

EP2482320A2 Method of fabricating a deep trench insulated gate bipolar transistor 审中-公开
标题翻译： Verfahren zur Herstellung eines bipolaren Transistors mit tiefgrabenisoliertem Gate
公开(公告)号：EP2482320A2
公开(公告)日：2012-08-01
申请号：EP12164824.0
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L21/331 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
摘要翻译：在一个实施例中，一种方法包括在相反导电类型的衬底上形成外延层，该外延层被缓冲层隔开，该缓冲层的垂直方向上的缓冲层的掺杂浓度基本上是恒定的。至少在缓冲层中，从外延层的顶表面在外延层中形成一对间隔开的沟槽。介电材料形成在第一和第二侧壁部分上的沟槽中。源极/集电极和主体区域形成在外延层的顶部，体区域将柱的源极/集电极区域与从体区域延伸到缓冲层的外延层的漂移区域分离。然后在与身体区域相邻并与其绝缘的每个沟槽中形成绝缘门构件。

16. 发明授权

EP1959500B1 High-voltage vertical FET and method of manufacturing the same 有权
标题翻译：立式高压FET和过程及其制备方法
公开(公告)号：EP1959500B1
公开(公告)日：2011-06-15
申请号：EP07254619.5
申请日：2007-11-28
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L29/423 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： A transistor fabricated on a semiconductor die is arranged into sections (36) of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die (25). Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.

17. 发明公开

EP2200088A1 Method of fabricating a deep trench insulated gate bipolar transistor 审中-公开
标题翻译：一种用于生产具有栅极tiefgrabenisoliertem双极晶体管过程
公开(公告)号：EP2200088A1
公开(公告)日：2010-06-23
申请号：EP09179794.4
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

18. 发明公开

EP1959500A3 High-voltage vertical FET 有权
标题翻译：高压垂直FET
公开(公告)号：EP1959500A3
公开(公告)日：2009-06-03
申请号：EP07254619.5
申请日：2007-11-28
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay
IPC分类号： H01L29/78 , H01L29/423 , H01L29/40 , H01L21/77
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： A transistor fabricated on a semiconductor die is arranged into sections (36) of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die (25). Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.
摘要翻译：在半导体管芯上制造的晶体管被布置成细长晶体管部分的部分（36）。这些部分基本上横跨半导体管芯（25）排列成行和列。一行或一列中的相邻部分被定向为使得相邻部分中的第一部分中的晶体管部分的长度沿第一方向延伸，并且相邻部分中的第二部分中的晶体管部分的长度以第二方向，第一方向基本上正交于第二方向。

19. 发明公开

EP1959497A3 High-voltage vertical FET 有权
标题翻译：立式高压FET
公开(公告)号：EP1959497A3
公开(公告)日：2009-06-03
申请号：EP07254019.8
申请日：2007-10-10
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit , Manley, Martin H.
IPC分类号： H01L29/78 , H01L29/423 , H01L29/40 , H01L21/77
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： A transistor fabricated on a semiconductor die (25) is arranged into sections (36) of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.

20. 发明公开

EP2482321A3 Method of fabricating a deep trench insulated gate bipolar transistor 审中-公开
标题翻译：一种用于生产具有栅极tiefgrabenisoliertem双极晶体管过程
公开(公告)号：EP2482321A3
公开(公告)日：2013-12-04
申请号：EP12164827.3
申请日：2009-12-18
申请人： Power Integrations, Inc.
发明人： Parthasarathy, Vijay , Banerjee, Sujit
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

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