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11. 发明授权

EP0072414B1 Dynamic semiconductor memory cell 失效
标题翻译：动态半导体存储单元
公开(公告)号：EP0072414B1
公开(公告)日：1988-01-13
申请号：EP82105776.7
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Eardley, David Barry , Gaur, Santosh Prasad
IPC分类号： G11C11/34 , H01L27/10
CPC分类号： H01L27/1028 , G11C11/34

12. 发明授权

EP0065133B1 Schottky barrier diode with a guard ring and method of making same 有权
标题翻译：带保护环的肖特基阻挡二极管及其制造方法
公开(公告)号：EP0065133B1
公开(公告)日：1988-01-07
申请号：EP82103562.3
申请日：1982-04-27
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad , Mauer IV, John Lester
IPC分类号： H01L29/91
CPC分类号： H01L29/872

13. 发明授权

EP0072412B1 Dynamic semiconductor memory cell 失效
标题翻译：动态半导体存储单元
公开(公告)号：EP0072412B1
公开(公告)日：1986-10-22
申请号：EP82105757.7
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad
IPC分类号： H01L27/10 , G11C11/24
CPC分类号： H01L27/1023 , G11C11/34 , H01L27/1028 , H01L27/115

14. 发明公开

EP0072414A3 Dynamic semiconductor memory cell 失效
标题翻译：动态半导体存储单元
公开(公告)号：EP0072414A3
公开(公告)日：1986-06-11
申请号：EP82105776
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Eardley, David Barry , Gaur, Santosh Prasad
IPC分类号： G11C11/34 , H01L27/10
CPC分类号： H01L27/1028 , G11C11/34
摘要： A single device dynamic semiconductor memory is formed having a P-type conductivity injector region (72) with hligh-low-high junctions of N-type conductivity disposed below the injector region. Those junctions trap injected minority charges which are detected by sensing the current flow from a source region (68) to a drain regions (51) which are located on opposite sides of the injector region (72). The source (68) and injector region (72) utilize ohmic contact while the low barrier Schottky contact (80) is made to the drain region (51). in order to provide separation between the depletion region of the Schottky contact (80) and the injector region (72), a heavily doped N (22) region is provided.
摘要翻译：单个器件动态半导体存储器形成为具有设置在注入区下方的具有N型导电性的高 - 低 - 高结的P型导电注入区（72）。那些结俘获注入的少数电荷，这些少数电荷通过感测从源区域（68）到位于注入区域（72）的相对侧上的漏极区域（51）的电流而被检测到。源极（68）和注入区（72）利用欧姆接触，而低阻挡肖特基接触（80）形成于漏极区（51）。为了提供肖特基接触（80）的耗尽区与注入区（72）之间的分隔，提供重掺杂N（22）区。

15. 发明公开

EP0089503A2 Method for making a high performance bipolar transistor in an integrated circuit 失效
标题翻译：一种用于在集成电路中制造高品质的双极型晶体管的方法。
公开(公告)号：EP0089503A2
公开(公告)日：1983-09-28
申请号：EP83101755.3
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Gaur, Santosh Prasad , Lechaton, John S. , Srinivasan, Gurumakonda R.
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/1004 , H01L21/3065 , H01L29/7325
摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

16. 发明公开

EP0072414A2 Dynamic semiconductor memory cell 失效
标题翻译： Dynamische Halbleiterspeicherzelle。
公开(公告)号：EP0072414A2
公开(公告)日：1983-02-23
申请号：EP82105776.7
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Eardley, David Barry , Gaur, Santosh Prasad
IPC分类号： G11C11/34 , H01L27/10
CPC分类号： H01L27/1028 , G11C11/34
摘要： A single device dynamic semiconductor memory is formed having a P-type conductivity injector region (72) with hligh-low-high junctions of N-type conductivity disposed below the injector region. Those junctions trap injected minority charges which are detected by sensing the current flow from a source region (68) to a drain regions (51) which are located on opposite sides of the injector region (72). The source (68) and injector region (72) utilize ohmic contact while the low barrier Schottky contact (80) is made to the drain region (51). in order to provide separation between the depletion region of the Schottky contact (80) and the injector region (72), a heavily doped N (22) region is provided.
摘要翻译：形成具有设置在注射器区域下方的具有N型导电体的高低接合点的P型电导率注入区域（72）的单一器件动态半导体存储器。这些接合捕获注入的少量电荷，这些电荷通过感测从源极区域（68）到位于注入器区域（72）的相对侧上的漏极区域（51）的电流来检测。源极（68）和注入器区域（72）利用欧姆接触，同时将低阻挡肖特基接触（80）制成漏极区域（51）。为了提供肖特基接触（80）的耗尽区与喷射区（72）之间的分离，提供了重掺杂的N（22）区域。

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