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11. 发明公开

EP4089531A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP4089531A1
公开(公告)日：2022-11-16
申请号：EP22180798.5
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/38 , G06F12/08
摘要： The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

12. 发明公开

EP3905039A1 VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM 有权
公开(公告)号：EP3905039A1
公开(公告)日：2021-11-03
申请号：EP21163280.7
申请日：2006-01-10
申请人： INTEL Corporation
发明人： BENNETT, Steven , ANDERSON, Andrew , NEIGER, Gilbert , SANKARAN, Rajesh , SMITH, Larry , UHLIG, Richard , RODGERS, Dion
IPC分类号： G06F9/455 , G06F12/109
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

13. 发明公开

EP3761210A1 CRYPTOGRAPHIC COMPUTING USING ENCRYPTED BASE ADDRESSES AND USED IN MULTI-TENANT ENVIRONMENTS 有权
公开(公告)号：EP3761210A1
公开(公告)日：2021-01-06
申请号：EP20168972.6
申请日：2020-03-17
申请人： Intel Corporation
发明人： NEIGER, Gilbert , DURHAM, David M , BRANDT, Jason , LEMAY, Michael , JAYARAM MASTI, Ramya
IPC分类号： G06F21/79 , G06F12/02 , G06F21/60 , G06F21/78
摘要： Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

14. 发明公开

EP3572937A1 VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM 有权
公开(公告)号：EP3572937A1
公开(公告)日：2019-11-27
申请号：EP19160715.9
申请日：2006-01-10
申请人： Intel Corporation
发明人： BENNETT, Steven , ANDERSON, Andrew , NEIGER, Gilbert , SANKARAN, Rajesh , SMITH, Larry , UHLIG, Richard , ROGERS, Dion
IPC分类号： G06F9/455
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

15. 发明授权

EP3210123B1 MEMORY PROTECTION KEY ARCHITECTURE WITH INDEPENDENT USER AND SUPERVISOR DOMAINS 有权
公开(公告)号：EP3210123B1
公开(公告)日：2019-07-03
申请号：EP15851712.8
申请日：2015-08-19
申请人： Intel Corporation
发明人： KOUFATY, David, A. , NEIGER, Gilbert , SANKARAN, Rajesh, M. , ANDERSON, Andrew, V. , DULLOOR, Subramanya, R. , HAAS, Werner , NUZMAN, Joseph
IPC分类号： G06F12/14 , G06F12/10 , G06F21/52

16. 发明公开

EP3198402A1 AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS 有权
标题翻译：避免早期从例外返回时启用无法中断的中断
公开(公告)号：EP3198402A1
公开(公告)日：2017-08-02
申请号：EP15843881.2
申请日：2015-08-31
申请人： Intel Corporation
发明人： ANVIN, H. Peter , NEIGER, Gilbert
IPC分类号： G06F9/30
CPC分类号： G06F13/24 , G06F9/327 , G06F9/4812 , G11C7/1072
摘要： A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.
摘要翻译：一个方面的处理器包括用于解码异常处理程序返回指令的解码单元。处理器还包括与解码单元耦合的异常处理程序返回执行单元。响应于异常处理程序返回指令，异常处理程序返回执行单元将不配置处理器以使得能够在NMI处理程序将后续接收到的不可屏蔽中断（NMI）传递给NMI处理程序，如果与异常处理程序返回指令相对应的异常，在NMI处理程序内被采取。响应于异常处理程序返回指令，异常处理程序返回执行单元将配置处理器，以使得如果在NMI处理程序中未采取异常，则能够将随后接收到的NMI传送到NMI处理程序。公开了其他处理器，方法，系统和指令。

17. 发明公开

EP1839142A1 SYSTEM AND METHOD TO DEPRIVILEGE COMPONENTS OF A VIRTUAL MACHINE MONITOR 审中-公开
标题翻译：系统和方法组件的虚拟计算机控制装置的ENTPRIVILIGIEREN
公开(公告)号：EP1839142A1
公开(公告)日：2007-10-03
申请号：EP05853583.2
申请日：2005-12-09
申请人： INTEL CORPORATION
发明人： ANDERSON, Andrew , BENNETT, Steven , COTA-ROBLES, Erik , KAGI, Alain , NEIGER, Gilbert , MADUKKARUMUKUMANA, Rajesh , SCHOENBERG, Sebastian , UHLIG, Richard , ROTHMAN, Michael , ZIMMER, Vincent , JEYASHINGH, Stalinselvaraj
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： In some embodiments, the invention involves a system to deprivilege components of a virtual machine monitor and enable deprivileged service virtual machines (SVMSs) to handle selected trapped events. An embodiment of the invention is a hybrid VMM operating on a platform with hardware virtualization support. The hybrid VMM utilizes features from both hypervisor-based and host-based VMM architectures. In at least one embodiment, the functionality of a traditional VMM is partitioned into a small platform-dependent part called a micro-hypervisor (MH) and one o more platform-independent parts called service virtual machines (SVMs). The micro-hypervisor operates at a higher virtual machine (VM) privilege level than any SVM, while the SVM and other VM’s may still have access to any instruction set architecture (ISA) privilege level. Other embodiments are described and claimed.

18. 发明公开

EP1735710A2 PROVIDING SUPPORT FOR SINGLE STEPPING A VIRTUAL MACHINE IN A VIRTUAL MACHINE ENVIRONMENT 审中-公开
标题翻译：提供支持，通过虚拟机传递一个虚拟机环境
公开(公告)号：EP1735710A2
公开(公告)日：2006-12-27
申请号：EP05730850.4
申请日：2005-03-25
申请人： Intel Corporation
发明人： BENNETT, Steven M. , ANDERSON, Andrew V. , COTA-ROBLES, Erik , JEYASINGH, Stalinselvaraj , KAGI, Alain , NEIGER, Gilbert , UHLIG, Richard , MONDAL, Sanjoy, K. , BRANDT, Jason
IPC分类号： G06F11/36
CPC分类号： G06F11/3664 , G06F9/45558 , G06F2009/45579 , G06F2009/45591
摘要： In one embodiment, a method induces receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a single-stepping indicator is set to a single stepping value, and transitioning control to the VM. Further, if an execution of a first instruction in the VM completes successfully, control is transitioned to the VMM following the successful completion of the execution of the first instruction.

19. 发明公开

EP1730633A1 METHOD AND APPARATUS FOR FACILITATING RECOGNITION OF AN OPEN EVENT WINDOW DURING OPERATION OF GUEST SOFTWARE IN A VIRTUAL MACHINE ENVIRONMENT 审中-公开
标题翻译：方法和设备，用于使打开的窗口事件的检测在操作过程中客户软件在虚拟机环境
公开(公告)号：EP1730633A1
公开(公告)日：2006-12-13
申请号：EP05731536.8
申请日：2005-03-28
申请人： Intel Corporation
发明人： BENNETT, Steven, M. , ANDERSON, Andrew, V. , COTA-ROBLES, Erik, C. , JEYASINGH, Stalinselvaraj , KÄGI, Alain , NEIGER, Gilbert , UHLIG, Richard, A.
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/45558 , G06F2009/45591
摘要： In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open.

20. 发明公开

EP4394589A1 RESTRICTING VECTOR LENGTH IN A PROCESSOR 审中-公开
公开(公告)号：EP4394589A1
公开(公告)日：2024-07-03
申请号：EP23195428.0
申请日：2023-09-05
申请人： Intel Corporation
发明人： SANJEEPAN, Vivekananthan , NEIGER, Gilbert , ESPIG, Michael
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30189
摘要： Techniques to restrict vector length in a processor are described. A method of an aspect that may be performed by a processor includes executing first instances of vector instructions having respective opcode values regardless of whether they specify wider vectors of a wider vector width or narrower vectors of a narrower vector width, when a control value is a first value. The method also includes executing second instances of vector instructions having the respective opcode values when they specify narrower vectors of the narrower vector width, but do not specify wider vectors of the wider vector width, when the control value is a second different value. The method also includes preventing execution of third instances of vector instructions having the respective opcode values when they specify wider vectors of the wider vector width, when the control value is the second value. Other methods, processors, and systems are disclosed.

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