会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 143. 发明公开
    • Clock generator for generating an accurate and low-jitter clock
    • 发电机zur Erzeugung eines Taktsignals mit geringem抖动
    • EP1394949A1
    • 2004-03-03
    • EP03254586.5
    • 2003-07-23
    • FUJITSU LIMITED
    • Tamura, Hirota Fujitsu Limited
    • H03L7/087
    • H03L7/087H03L7/07H03L7/0812H03L7/0891H03L7/091H03L7/093H04L7/033
    • A clock generator has a clock generating circuit (5), a phase difference detection circuit (1, 7), and a control signal generating circuit (3, 4, 9). The clock generating circuit has a function for varying a clock phase in accordance with a control signal. The phase difference detection circuit compares the clock phase output from the clock generating circuit with a phase of a reference waveform, and detects a phase difference therebetween. The control signal generating circuit generates a control signal for controlling the clock phase of the clock generating circuit, based on phase difference information obtained from the phase difference detection circuit. The phase difference detection circuit has a plurality of phase detection units. At least one of the plurality of phase detection units carries out a direct phase detection in which a phase of the clock is directly compared with the phase of the reference waveform, and at least the other one of the plurality of phase detection units carries out an indirect phase detection using a phase-synchronized waveform generating circuit (6) generating a waveform synchronized in phase with the reference waveform or an output of the clock generating circuit and a phase information extracting circuit extracting phase information from the phase-synchronized waveform.
    • 时钟发生器具有时钟发生电路(5),相位差检测电路(1,7)和控制信号发生电路(3,4,9)。 时钟发生电路具有根据控制信号改变时钟相位的功能。 相位差检测电路将来自时钟发生电路的时钟相位输出与参考波形的相位进行比较,并检测它们之间的相位差。 控制信号发生电路根据从相位差检测电路得到的相位差信息,生成用于控制时钟发生电路的时钟相位的控制信号。 相位差检测电路具有多个相位检测单元。 多个相位检测单元中的至少一个执行直接相位检测,其中时钟的相位与参考波形的相位直接比较,并且多个相位检测单元中的至少另一个相位检测单元执行 使用产生与参考波形同步的波形或时钟发生电路的输出的相位同步波形发生电路(6)进行间接相位检测,以及从相位同步波形提取相位信息的相位信息提取电路。
    • 145. 发明公开
    • Plasma display panel
    • 等离子体Anzeigetafel
    • EP1361595A2
    • 2003-11-12
    • EP03252797.0
    • 2003-05-02
    • Fujitsu Hitachi Plasma Display Limited
    • Harada, Hideki, Fujitsu Hitachi Plasma Display Ltd
    • H01J17/49
    • H01J11/12H01J11/46H01J11/48
    • An AC plasma display panel is disclosed having a pair of panels (1,2) disposed in spaced opposed relation, and each having a plurality of electrodes (11,21) formed on an opposed surface thereof and mostly covered with a dielectric layer (13,23); and a sealing member (3) which seals the periphery of the pair of panels (1,2). The electrodes (11,21) each have a portion uncovered with the dielectric layer (13,23), and the sealing member (3) is disposed in contact with the uncovered portions of the electrodes (11,21). With this arrangement, the discharge space can be kept gas-tightly sealed by the sealing member (3) without communication with the outside of the display panel which may otherwise occur due to the presence of voids on opposite sides and surfaces of the electrodes (11,21).
    • 公开了一种交流等离子体显示面板,其具有以对置的间隔设置的一对面板(1,2),并且每个具有形成在其相对表面上的多个电极(11,21),并且主要被电介质层(13 ,23); 以及密封所述一对面板(1,2)的周边的密封构件(3)。 电极(11,21)各自具有未被电介质层(13,23)覆盖的部分,并且密封构件(3)设置成与电极(11,21)的未覆盖部分接触。 通过这种布置,放电空间可以由密封构件(3)保持气密密封,而不与显示面板的外部连通,否则可能由于在电极(11)的相对侧和表面上存在空隙而发生 ,21)。