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111. 发明公开

EP0902436A2 Microcomputer with flash memory programmable via external terminal 失效
标题翻译：微机与外部连接端子可编程闪存
公开(公告)号：EP0902436A2
公开(公告)日：1999-03-17
申请号：EP98118739.6
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06 , G06F9/445
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

112. 发明公开

EP0893799A2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：与无干扰的数据线划分快闪存储器及微型电子计算机，以便存储块
公开(公告)号：EP0893799A2
公开(公告)日：1999-01-27
申请号：EP98118740.4
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device on a semiconductor chip comprises an address bus (ABUS), a data bus (DBUS, HDBUS, LDBUS), a central processing unit (CPU) being capable of processing data of a plurality of bits, and a flash memory (FMRY) having a plurality of memory cells (MC) arranged so as to be simultaneously erasable, said flash memory including a plurality of memory arrays (ARY0-ARY7) and being responsive to accessing from said central processing unit via said address bus and providing one data of a plurality of bits within a plurality of data stored therein to said central processing unit via said data bus in a manner in which each memory array outputs one bit (D0-C7) of said plurality of bits constituting said one data.
摘要翻译：一半导体芯片的地址总线的包括（ABUS），数据总线（DBUS，HDBUS，LDBUS），能够比特的多个处理数据的中央处理单元（CPU），和一个闪速存储器上的一个半导体集成电路器件（FMRY）具有存储单元（MC）排列的多个，以便同时擦除，所述闪存存储器包括存储器阵列（ARY0-ARY7）的多元并响应于通过所述地址总线从所述中央处理单元访问，并提供位的经由所述数据总线存储在其中，以所述中央处理单元在所述多个位中的每存储器阵列输出的一个位（D0-C7）构成所述一个数据，其中一个方式的数据内的多个的多个一个数据。

113. 发明公开

EP0854509A1 Fabrication method for non-volatile memory with high-voltage and logic components 失效
标题翻译：用于非易失性存储器具有高电压和逻辑器件的制造工艺
公开(公告)号：EP0854509A1
公开(公告)日：1998-07-22
申请号：EP98100462.5
申请日：1998-01-13
申请人： Programmable Microelectronics Corporation
发明人： Chang, Shang-De Ted, Progr. Microelectronics Corp. , Ly, Binh, Programmable Microelectronics Corp.
IPC分类号： H01L21/8239
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.
摘要翻译：一种半导体制造工艺允许高电压晶体管，逻辑晶体管和存储单元的制造，其中，根据需要用于子0.3微米设备的几何形状，所述逻辑晶体管的栅极氧化比非的隧道氧化物厚度薄易失性存储器细胞，而不在存储器单元的隧道氧化物的逻辑晶体管或污染的栅极氧化物的不希望的污染。在一个，实施例的存储器单元的隧道氧化物生长到厚度希望的。在下一步骤中的，而这些用作存储单元（多个）的浮栅掺杂的多晶硅层被立即沉积在存储器单元的隧道氧化物，由此保护隧道氧化物从污染在随后的掩模和蚀刻步骤。则逻辑晶体管和高电压晶体管的栅氧化物的栅氧化层生长到厚度希望的。

114. 发明授权

EP0613176B1 Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection 失效
标题翻译：用于生产的集成器件，包括非易失性存储器和与隧道氧化物保护晶体管
公开(公告)号：EP0613176B1
公开(公告)日：1997-07-30
申请号：EP93830057.1
申请日：1993-02-17
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Cappelletti, Paolo Giuseppe
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11521 , H01L27/11541 , H01L27/11546 , Y10S438/979
摘要： A process for simultaneously fabricating memory cells (2), transistors, and diodes (3) for protecting the tunnel oxide layer (9) of the cells, using the DPCC process wherein the first polysilicon layer (poly1, 10) is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first (10) and second (13) polysilicon layers. To form the diodes, the poly1 layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping poly1; the interpoly dielectric layer (11) and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer (poly2) is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions (6) which, together with the substrate (4), constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates (12) of the cells by the second polycrystalline silicon layer strips forming the word lines.

115. 发明授权

EP0443610B1 Nonvolatile semiconductor memory device 失效
标题翻译：的非易失性半导体存储器件
公开(公告)号：EP0443610B1
公开(公告)日：1997-05-02
申请号：EP91102635.9
申请日：1991-02-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Wada, Masashi, c/o Intellectual Property Division
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/16 , H01L27/11546
摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array (311) composed of a collection of blocks (313-1, 313-2, ..., 313-n), each block containing memory cells sharing the source or drain, a first region (302) having the memory cell array formed in its surface region, and a control circuit (312) that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential (VS1, ..., VSn, VS1', ..., VSn') and the first region at a second potential (VW) higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential (VG11, ..., VGn, VG1', ..., VGn') equal to or higher than the second potential and lower than the first potential.

116. 发明公开

EP0751559A1 Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 失效
标题翻译：包含非易失性存储器单元和外围晶体管，和相应的类型的集成电路的电路的制造方法
公开(公告)号：EP0751559A1
公开(公告)日：1997-01-02
申请号：EP95830281.2
申请日：1995-06-30
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Clementi, Cesare , Ghidini, Gabriella , Riva, Carlo
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for:

removal of said layers from the peripheral zones (R2) of the matrix;
deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and
formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2).

To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.
摘要翻译：一种用于形成对集成电路工艺要求提供（1）在中间电介质多层具有包含非易失性存储器单元中的至少一个矩阵的至少一个下电介质材料层（8），并在上部氧化硅层（9）和在区域周向具有第一厚度的栅极介电的至少一个第一晶体管类型（2）的基体中的同时提供。与栅极氧化物层（4）和多晶硅层（5）和下电介质材料层的形成在形成浮置栅极之后（8），在雅舞蹈过程与本发明要求：去除所述层的从基体的外周区域（R2）; 说，在存储单元（1）上的氧化硅层（9）的沉积，并用在外围晶体管（2）的区域（R2）的基板（3）; 和形成在外围晶体管（2）的区域（R2）的至少一个第一氧化硅层（10）的。以提供另外具有第二厚度的栅极介电的第二晶体管的类型，指示性比所述第一厚度薄，在雅舞蹈添加与本发明的连续步骤。

117. 发明公开

EP0725980A1 METHOD OF FABRICATION OF AN INTEGRATED CIRCUIT CHIP CONTAINING EEPROM AND CAPACITOR 失效
标题翻译：过程执行EEPROM和一个电容含集成电路芯片
公开(公告)号：EP0725980A1
公开(公告)日：1996-08-14
申请号：EP95931647.0
申请日：1995-08-29
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： CACHARELIS, Philip, J. , PERRY, Jeffrey, R. , NARAHARI, Narasimha
IPC分类号： H01L21 , H01L27
CPC分类号： H01L27/11526 , H01L27/0611 , H01L27/0688 , H01L27/105 , H01L27/11529 , H01L27/11546 , H01L27/11551
摘要： An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

118. 发明公开

EP0542575A2 Method for fabricating a semiconductor memory device having a floating gate with improved insulation film quality 失效
标题翻译：一种用于制造半导体存储器件，其包括具有改善的绝缘层的浮置栅极的方法。
公开(公告)号：EP0542575A2
公开(公告)日：1993-05-19
申请号：EP92310402.0
申请日：1992-11-13
申请人： FUJITSU LIMITED
发明人： Kajita, Tatsuya, c/o Fujitsu Limited
IPC分类号： H01L21/82 , H01L27/115 , H01L29/62 , H01L29/788
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11543 , H01L27/11546 , H01L29/51
摘要： A method for fabricating a flash-EPROM comprises the steps of forming a first gate insulation film (24a) and a second gate insulation film (24b) on a semiconductor substrate so as to respectively cover first and second device regions, providing a first conductor layer (28) so as to cover both the first device region and the second device region, patterning the first conductor layer to form a floating gate electrode (28a) in correspondence to the first device region, oxidizing a surface of the first conductor layer to form a capacitor insulation film (30c) surrounding the floating gate electrode, providing a second conductor layer (31) on the first conductor layer as to bury underneath the floating gate electrode covered by the capacitor insulation film, patterning the second conductor layer on the first device region to form a control gate electrode (31a), exposing the first conductor layer in correspondence to the second device region, and patterning the first conductor layer remaining on the second element region to form a gate electrode of a peripheral transistor.
摘要翻译：一种用于制造闪存EPROM方法包括形成第一栅绝缘膜 - （24A）和第二栅极绝缘膜 - 的步骤（24B）上的半导体基板，以分别覆盖第一和第二器件区域，提供第一导体层（28），以便覆盖所述第一器件区和第二器件区域，图案化所述第一导体层，以形成对应于所述第一器件区域中的浮栅电极（28A），氧化所述第一导体层的表面上以形成围绕所述浮置栅电极，在所述第一导体层上提供的第二导体层（31），以由电容绝缘膜，电影覆盖浮置栅电极下面掩埋，在第一设备上图案化所述第二导体层的电容器绝缘膜 - （30℃）区域，以形成控制栅电极（31），暴露对应于所述第一导体层的第二器件区域，和图案化所述第一导体层remainin 在第二元件区域g以形成外围晶体管的栅电极。

119. 发明授权

EP0085551B1 Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein 失效
标题翻译：制造具有可编程和电可擦除存储器件的MOS存储器阵列的方法
公开(公告)号：EP0085551B1
公开(公告)日：1990-10-24
申请号：EP83300451.8
申请日：1983-01-28
申请人： SEEQ TECHNOLOGY, INCORPORATED
发明人： Chiu, Te-Long
IPC分类号： H01L29/60 , G11C11/34
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546
摘要： A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling regions (20, 78) are formed in the substrate (8, 71) and thin tunnel dielectrics (22, 84) comprised of silicon dioxide/oxynitride material are grown over the tunneling regions (20, 78) to facilitate transport of charge carriers between the tunneling regions (20, 78) and subsequently-fashioned floating gate structures (14R, 14L, 156) in the memory cells (2, 198, 200). A first layer of doped polycrystalline silicon is then deposited over the substrate and etched to define large polysilicon areas. An oxide layer is grown over the large polysilicon areas in a manner such that out-diffusion of the impurity present in the large polysilicon areas is prevented. Thereafter, a second layer of doped polycrystalline silicon is deposited over the substrate and etched together with the large polysilicon areas to define the memory cell floating gate structures (14 R, 14L, 156) as well as various memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and peripheral device control gates (136, 138). Source and drain regions (34, 36, 58, 60, 64, 66, 168-179) for the memory cells (2, 198, 200) and the peripheral devices (202, 204, 206) are established by implanting an impurity in the semiconductor substrate (8, 71), using the memory cell program and control gates (16R, 16L, 40R, 40L, 128, 132) and the peripheral device control gates (136, 138) for alignment. Protective coverings of refill oxide (188) and VapOx (190) are formed over the substrate to complete the fabrication process.

120. 发明授权

EP2423952B1 Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area 有权转让
公开(公告)号：EP2423952B1
公开(公告)日：2018-10-10
申请号：EP11176611.9
申请日：2011-08-04
申请人： NXP USA, Inc.
发明人： Shroff, Mehul D.
IPC分类号： H01L21/28 , H01L29/423 , H01L29/788 , H01L27/115 , H01L27/11534 , H01L27/11546
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11534 , H01L27/11546 , H01L29/42328 , H01L29/42332
摘要： Forming a gate stack of a non-volatile memory (NVM) over a substrate (84) having an NVM region (82) and non-NVM region (80) which does not overlap the NVM region includes forming a select gate layer (92) over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer (96) over the substrate in the NVM and non-NVM regions; forming a control gate layer (98) over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.

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