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101. 发明公开

EP3101546A1 PROVIDING FAILOVER CONTROL ON A CONTROL SYSTEM 有权
标题翻译： AUSFALLSICHERUNGSBEREITSTELLUNG在EINEM STEUERUNGSSYSTEM
公开(公告)号：EP3101546A1
公开(公告)日：2016-12-07
申请号：EP16167689.5
申请日：2016-04-29
申请人： GE Aviation Systems LLC
发明人： LASSINI, Stefano A. M. , THERIAULT, Timothy John , DARNELL, Mark Lawrence
IPC分类号： G06F11/16 , G06F11/20
CPC分类号： G06F11/2033 , B64C13/50 , G06F11/00 , G06F11/1645 , G06F11/184 , G06F11/2025 , G06F11/2028 , G06F2201/805 , G07C5/0808
摘要： Systems and methods for providing failover control in a control system are provided. For instance, a data stream 124 from a plurality of computing nodes 102, 104 in a computing system 100 can be monitored. A first subset of computing nodes 102, 104 can be selected based on the data streams 124. Control grant signals can be generated for each computing node 102, 104 of the first subset. An output to one or more computing nodes 102, 104 of the first subset can be activated based at least in part on a number of control grant signals generated for each computing node 102, 104 of the first subset. Control authority can then be granted to the one or more computing nodes 102, 104 of the first subset.
摘要翻译：提供了在控制系统中提供故障转移控制的系统和方法。例如，可以监视来自计算系统100中的多个计算节点102,104的数据流124。可以基于数据流124来选择计算节点102,104的第一子集。可以为第一子集的每个计算节点102,104生成控制授权信号。至少部分地基于为第一子集的每个计算节点102,104生成的控制许可信号的数量来激活到第一子集的一个或多个计算节点102,104的输出。然后可以将控制权限授予第一子集的一个或多个计算节点102,104。

102. 发明授权

EP2648102B1 Dispositif pour la détermination d'informations de localisation et de références primaires inertielles pour un aéronef 失效
标题翻译：装置用于确定飞行器的位置信息和所述原惯性参考值
公开(公告)号：EP2648102B1
公开(公告)日：2016-05-25
申请号：EP13162611.1
申请日：2013-04-05
申请人： Thales
发明人： Arethens, Jean-Pierre , Bouard, Dominique
IPC分类号： G06F11/18 , G01S19/45 , G01S19/47
CPC分类号： G01C21/005 , G01C21/10 , G01C21/20 , G01C23/005 , G01S19/45 , G01S19/47 , G06F11/1487 , G06F11/1645 , G06F11/185

103. 发明授权

EP2629202B1 Method of providing high integrity processing 有权
标题翻译：提供高完整性处理的方法
公开(公告)号：EP2629202B1
公开(公告)日：2014-09-24
申请号：EP12192319.7
申请日：2012-11-13
申请人： GE Aviation Systems LLC
发明人： Theriault, Bryan A , Diekema, Jon Marc , Coviak, Kenneth Lewis , Plante, Steven Edward
IPC分类号： G06F11/16
CPC分类号： G06F11/1683 , G06F11/1645

104. 发明授权

EP2513796B1 VERFAHREN ZUM BETREIBEN EINER RECHENEINHEIT 有权
标题翻译：一种用于操作BUTTERFLY
公开(公告)号：EP2513796B1
公开(公告)日：2013-10-02
申请号：EP10788296.1
申请日：2010-12-02
申请人： Robert Bosch GmbH
发明人： MUELLER, Bernd , FERCH, Markus , COLLANI, Yorck , BANSKI, Holger
IPC分类号： G06F11/16 , G06F11/07 , G06F11/14
CPC分类号： G06F11/1695 , G06F11/0715 , G06F11/0724 , G06F11/0739 , G06F11/0757 , G06F11/1487 , G06F11/1633 , G06F11/1645 , G06F11/1654 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F2201/83
摘要： A method for operating an arithmetic unit having at least two computation cores. One signature register which has multiple inputs is assigned in each case to at least two of the at least two computation cores. At least one task is executed by the at least two of the at least two computation cores, an algorithm is computed in each task, results computed by each computation core are written into the assigned signature register, and the results written into the signature registers are compared.

105. 发明公开

EP2537091A1 DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR 审中-公开
标题翻译：数据处理，数据处理装置及设备与数据处理
公开(公告)号：EP2537091A1
公开(公告)日：2012-12-26
申请号：EP10846024.7
申请日：2010-02-16
申请人： Freescale Semiconductor, Inc.
发明人： ROHLEDER, Michael , FADER, Joachim , LENKE, Frank , BAUMEISTER, Markus
IPC分类号： G06F9/38 , G06F9/28 , G06F9/46
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation (405), and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation (401 ). The non-synchronised redundant operation (401 ) comprises an initial performance (402) of the selected identical data processing steps in one of the data processing units and a replicate performance (404) of the data processing steps starting later than the initial performance (402), preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered (412, 414), and compared (434) with replicate result data representative of results from the replicate performance (404), and an error signal (434) is produced in case of discrepancy.

106. 发明公开

EP2513796A1 VERFAHREN ZUM BETREIBEN EINER RECHENEINHEIT 有权
标题翻译：一种用于操作BUTTERFLY
公开(公告)号：EP2513796A1
公开(公告)日：2012-10-24
申请号：EP10788296.1
申请日：2010-12-02
申请人： Robert Bosch GmbH
发明人： MUELLER, Bernd , FERCH, Markus , COLLANI, Yorck , BANSKI, Holger
IPC分类号： G06F11/16
CPC分类号： G06F11/1695 , G06F11/0715 , G06F11/0724 , G06F11/0739 , G06F11/0757 , G06F11/1487 , G06F11/1633 , G06F11/1645 , G06F11/1654 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F2201/83
摘要： A method for operating an arithmetic unit having at least two computation cores. One signature register which has multiple inputs is assigned in each case to at least two of the at least two computation cores. At least one task is executed by the at least two of the at least two computation cores, an algorithm is computed in each task, results computed by each computation core are written into the assigned signature register, and the results written into the signature registers are compared.

107. 发明公开

EP2423818A1 ASYNCHRONOUS REMOTE COPY SYSTEM AND STORAGE CONTROL METHOD 失效
标题翻译：异教徒飞行员
公开(公告)号：EP2423818A1
公开(公告)日：2012-02-29
申请号：EP10841823.7
申请日：2010-04-07
申请人： Hitachi, Ltd.
发明人： KONDO, Shuji , OKUMOTO, Katsuhiro
IPC分类号： G06F12/00
CPC分类号： G06F11/1645 , G06F11/1456 , G06F11/2058 , G06F11/2074 , G06F11/2079 , G06F11/2082 , G06F2201/855
摘要： If the first storage apparatus is suspended, it is determined which of the update number which the journal recently reflected in the second storage apparatus comprises and the update number which the journal recently reflected in the third storage apparatus comprises is the newer. It is determined, in the newer storage apparatus which is determined to comprise the newer update number, whether one or more differential journals from the journal comprising the update number next to the update number which is not determined to be the newer to the journal comprising the update number determined to be the newer exist or not. If the result of the determination is positive, from the newer storage apparatus to the previous storage apparatus which is not the newer of the second and the third storage apparatuses, one or more differential JNLs are copied. In the previous storage apparatus, one or more differential JNLs are reflected in order of the update numbers, to the data volumes in the previous storage apparatus.
摘要翻译：如果第一存储装置被暂停，则确定最近在第二存储装置中反映的日志的更新号码中哪一个包括最近在第三存储装置中反映的日志的更新号码是较新的。确定在被确定为包括较新的更新号码的较新的存储装置中，是否包括来自包括更新号码旁边的更新号码的一个或多个差分日志，该更新号码未被确定为包括更新号码确定为较新的存在与否。如果确定结果是肯定的，则从较新的存储装置到不是第二和第三存储装置的较新的先前存储装置，复制一个或多个差分JNL。在先前的存储装置中，一个或多个差分JNL以更新号的顺序反映到先前存储装置中的数据量。

108. 发明授权

EP1989624B1 HIGH SPEED REDUNDANT DATA PROCESSING SYSTEM 有权转让
标题翻译：快速冗余数据处理系统
公开(公告)号：EP1989624B1
公开(公告)日：2010-01-20
申请号：EP06831395.6
申请日：2006-12-15
申请人： Eads Defence And Security Systems Limited
发明人： LEARMONTH, Darren, Stewart
IPC分类号： G06F11/16
CPC分类号： G06F11/1645
摘要： A high speed data processing system is described comprising first and second data processing modules and first and second data checking modules. The first and second data processing modules are each arranged to perform substantially the same processing steps on data received at said data input, with each providing an output. The first and second checking modules are arranged to compare the outputs of said first and second data processing modules and to output an error signal indicative of whether or not said first and second data processing modules have performed substantially the same processing steps. The first and second checking modules are located on physically separate devices. In some arrangements a third checking module is provided, which checking module may be physically separated from each of said first and second checking modules.

109. 发明公开

EP1484681A3 Rechnersystem mit einem Mastersystem, einem Slavesystem, und einer Datensychronisierungseinrichtung 审中-公开
标题翻译：一种计算机系统，具有一个主系统，从系统和Datensychronisierungseinrichtung
公开(公告)号：EP1484681A3
公开(公告)日：2009-01-28
申请号：EP04090129.0
申请日：2004-04-02
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Kendelbacher, Detlef , Pliquett, Volker , Stein, Fabrice
IPC分类号： G06F11/16
CPC分类号： G06F11/2048 , G06F11/1645 , G06F11/1658 , G06F11/1683 , G06F11/1687 , G06F11/2028 , G06F11/2033 , G06F11/2038 , G06F11/2097
摘要： Die Erfindung betrifft eine Rechneranordnung mit einem eigensicheren, als Mastersystem (A) konfigurierten 2v2 Rechnersystem und einem weiteren eigensicheren, mit dem Mastersystem (A) gekoppelten, als Slavesystem (B) konfigurierten, 2v2 Rechnersystem. Zur Erhöhung der Ausfalltoleranz ist vorgesehen, dass zwischen Master- und Slavesystem (A und B) eine erste Verbindung zwecks Synchronisierung der Eingabedaten vorgesehen ist, mittels der durch transaktionsorientierte Datenübertragung die Übereinstimmung der Ausgaben beider parallel arbeitender 2v2 Rechnersysteme sicherstellbar ist - Inputsynchronisierung - und dass eine zweite Verbindung zwecks Synchronisierung der Ausgabedaten vorgesehen ist, mittels der das Mastersystem (A) die Ausgaben des Slavesystems (B) in sicherer Art und Weise abschalten kann - Outputsynchronisierung.

110. 发明授权

EP0986008B1 Computer system comprising controllers and computing elements 失效
标题翻译：一种计算机系统，具有控制单元和计算机元件
公开(公告)号：EP0986008B1
公开(公告)日：2008-04-16
申请号：EP99122243.1
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F15/16 , G06F11/16 , G06F15/76 , G06F13/00 , G06F11/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

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