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91. 发明公开

EP0505877A2 Impurity doping method with adsorbed diffusion source 失效
标题翻译： Dotierungsverfahren手套einer adsorptionbierten Diffusionsquelle。
公开(公告)号：EP0505877A2
公开(公告)日：1992-09-30
申请号：EP92104495.4
申请日：1992-03-15
申请人： SEIKO INSTRUMENTS INC.
发明人： Akamine, Tadao, c/o Seiko Instruments Inc. , Saito, Naoto, c/o Seiko Instruments Inc. , Aoko, Kenji, c/o Seiko Instruments Inc.
IPC分类号： H01L21/225 , C30B31/02
CPC分类号： H01L21/2254 , H01L21/2225
摘要： The surface of a silicon wafer is cleaned to expose chemically active surface. Diborane gas is fed to the exposed active surface for adsorbing boron to the active surface. The adsorbed boron on the silicon wafer works as an impurity diffusion source. Boron is diffused from the impurity diffusion source into the silicon wafer to make an impurity diffusion layer by heat treatment. The amount of diborane gas to be fed to the active surface is set an amount of which sheet resistance of the impurity diffusion layer does not depend on.
摘要翻译：清洁硅晶片的表面以暴露化学活性表面。将二烷烃气体供给到暴露的活性表面，以将硼吸附到活性表面。硅晶片上吸附的硼作为杂质扩散源。硼从杂质扩散源扩散到硅晶片中，通过热处理形成杂质扩散层。供给到活性表面的乙硼烷气体的量设定为杂质扩散层的薄层电阻不依赖的量。

92. 发明公开

EP0491976A1 Verfahren zur Herstellung einer mit Arsen dotierten glatten polykristallinen Siliziumschicht für höchstintegrierte Schaltungen 失效
标题翻译：一种用于生产具有光滑的砷的多晶硅层掺杂的非常大规模集成电路工艺。
公开(公告)号：EP0491976A1
公开(公告)日：1992-07-01
申请号：EP90125289.0
申请日：1990-12-21
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Wild, Barbara, Dipl.-Ing.
IPC分类号： H01L21/225
CPC分类号： H01L29/66181 , H01L21/2257 , H01L21/32055 , H01L21/32155
摘要： Bei einem mehrstufigen Verfahren zur Herstellung einer insbesondere niedrig mit Arsen dotierten glatten polykristallinen Siliziumschicht für höchstintegrierte Schaltungen, durch thermische Zersetzung von die Elemente enthaltenden gasförmigen Verbindungen, werden direkt hintereinander eine oberflächendeckende, höchstens wenige Atome dicke Arsenschicht als Vorbelegung und auf diese anschließend eine undotierte amorphe Siliziumschicht bei einer Temperatur unterhalb von 580° C abgeschieden. Nachfolgend erfolgt eine gleichmäßige Dotierung der Siliziumschicht durch die als Diffusionsquelle dienende Arsenschicht durch eine Temperaturbehandlung, bei der gleichzeitig das amorphe Silizium zu einer polykristallinen Siliziumschicht ausgebildet wird. Der Druck bei der Vorbelegung wird auf 13 bis 20 Pa und die Temperatur bei Vorbelegung und Abscheidung auf etwa 550 bis 580 C eingestellt. Das Verfahren wird bei der Herstellung sehr eng benachbarter (16 Mbit-DRAM) grabenförmiger Kondensator-Speicherzellen verwendet.
摘要翻译：在用于特别轻轻通过含有气态化合物，直接连续，表面覆盖的元件的热分解掺杂有砷平滑多晶硅层对于超大规模集成电路的生产的多级过程中，在砷的最几个原子厚层作为缺省，并且这然后未掺杂的非晶硅层沉积在低于580℃的温度下以下是通过作为由温度处理，在其同时在非晶硅形成为多晶硅层的砷的扩散源层的硅层的均匀掺杂。在预分配的压力设定为13〜20 Pa和在预分配和淀积温度在约550-580℃。所述方法是在非常紧密间隔（16兆位DRAM）严重形电容器的存储单元的制造中使用。

93. 发明公开

EP0472012A2 Method of boron diffusion into semiconductor wafers 失效
标题翻译：在Halbleiterwafern的Verfahren zur Bor扩散。
公开(公告)号：EP0472012A2
公开(公告)日：1992-02-26
申请号：EP91112736.3
申请日：1991-07-29
申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED
发明人： Katayama, Masatake , Fujiya, Shoichi , Moroga, Isao , Shinomiya, Masaru
IPC分类号： H01L21/225 , H01L21/22
CPC分类号： H01L21/2254 , Y10S148/037 , Y10S438/909 , Y10S438/92
摘要： A method of diffusing boron into semiconductor wafers is disclosed which is made of essentially boron deposition and boron diffusion steps. The deposition step is performed from 900 to 1,000°C and the diffusion step at a temperature substantially equal to or higher than the temperature at the deposition step. Oxidation induced stacking faults are greatly reduced.
摘要翻译：公开了将硼扩散到半导体晶片中的方法，其基本上由硼沉积和硼扩散步骤制成。沉积步骤在900至1000℃下进行，扩散步骤在基本上等于或高于沉积步骤的温度的温度下进行。氧化引起的堆垛层错大大减少。

94. 发明公开

EP0459398A3 Manufacturing method of a channel in MOS semiconductor devices 失效
标题翻译： MOS半导体器件中的通道的制造方法
公开(公告)号：EP0459398A3
公开(公告)日：1992-01-08
申请号：EP91108692.4
申请日：1991-05-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toyoshima, Yoshiaki, c/o Intellectual Property Div , Eguchi, Tamao, c/o Intellectual Property Div.
IPC分类号： H01L29/784 , H01L29/10 , H01L21/225
CPC分类号： H01L29/66575 , H01L21/2256 , H01L29/1033 , H01L29/7838 , Y10S438/923
摘要： Formed on the element region (13) of an n-type semiconductor substrate (12) is a silicon oxide layer (14), on which a polysilicon layer (15) is formed. Boron ions, p-type impurities, are then implanted into the polysilicon layer (15), from which boron diffuses into the element region (13) via the silicon oxide layer (14), with the result that a p-channel region of the p-channel MOS transistor is formed.

95. 发明公开

EP0451553A3 Self-aligned silicided base bipolar transistor and resistor and method of fabrication 失效
标题翻译：自对准硅基双极晶体管和电阻器及其制造方法
公开(公告)号：EP0451553A3
公开(公告)日：1991-11-27
申请号：EP91104215.8
申请日：1991-03-19
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： DeLong, Bancherd , Ganschow, George , Blair, Christopher Scott , Crabb, Thomas Scott
IPC分类号： H01L27/06 , H01L21/225
CPC分类号： H01L28/20 , H01L21/28525 , H01L29/66272 , H01L29/6628 , Y10S148/123
摘要： A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.

96. 发明公开

EP0451553A2 Self-aligned silicided base bipolar transistor and resistor and method of fabrication 失效
标题翻译： Selbstjustierender Silizidbasisbipolartransistor und Widerstand und Herstellungsverfahren。
公开(公告)号：EP0451553A2
公开(公告)日：1991-10-16
申请号：EP91104215.8
申请日：1991-03-19
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： DeLong, Bancherd , Ganschow, George , Blair, Christopher Scott , Crabb, Thomas Scott
IPC分类号： H01L27/06 , H01L21/225
CPC分类号： H01L28/20 , H01L21/28525 , H01L29/66272 , H01L29/6628 , Y10S148/123
摘要： A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.
摘要翻译：提供了双极晶体管和电阻器。制造包括使用高温氧化物来形成用于晶体管触点的侧壁间隔件和/或覆盖器件的电阻器部分。 HTO的沉积与掺杂剂驱入相结合，因此需要更少的总步数。该过程与MOS技术兼容，使得双极晶体管和电阻器可以与MOS器件一起形成在衬底上。

97. 发明公开

EP0445059A2 Method for performing a complementary bipolar transistor structure including a self-aligned vertical PNP transistor 失效
标题翻译：一种制造互补双极型晶体管结构，其包括一个自对准垂直PNP晶体管的方法。
公开(公告)号：EP0445059A2
公开(公告)日：1991-09-04
申请号：EP91480017.2
申请日：1991-01-25
申请人： International Business Machines Corporation
发明人： Cook, Robert Kimball , Hsieh, Chang-Ming , Isihara, Kiyoshi
IPC分类号： H01L27/082 , H01L21/225 , H01L21/331
CPC分类号： H01L21/82285 , H01L27/0826 , Y10S148/011
摘要： The method includes the steps of: providing a substrate (10), of semiconductor material including at least two electrically isolated N-type device regions(26, 28) having a generally planar common surface; forming a P-type buried subcollector region (38, 40) in the first of the device regions; forming an N-type buried subcollector region (34, 36) in the second of the device regions; forming an N-type base region (42), in the common surface of the first device region; forming a layer (52) of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact (52C) generally centered on the base region of the first device region and a generally annular base contact (52D) on the second device region; forming a layer (66) of insulating materi-al over the patterned layer of P-doped polysilicon; forming a layer (71) of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a base contact (71B, 71C) generally surrounding the emitter contact on the first device region and an emitter contact (71C) generally surrounded by the base contact (52D) on the second device region; and heating the device at least once to drive impurities from the base and emitter contacts on the first and second device regions into the device regions whereby to form a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region.
摘要翻译：该方法包括以下步骤：提供半导体材料的基片（10），其包括具有基因反弹平面共同表面上的至少两个电隔离的N型器件区域（26，28）; 形成在所述装置的所述第一区域中的P型埋入区子集电极（38，40）; 形成在该装置的第二区域N型埋的子集电极区域（34，36）; 形成在所述第一器件区的公共表面的N型基极区域（42）; 形成P型掺杂的多晶硅上的在所述第一器件区和在所述第二器件区域中的基极区中的层（52）; 图案化P掺杂多晶硅层，以形成在发射极接触（52C）基因集会中心在第一器件区和基因反弹环形设计基极接触（52D）在所述第二器件区的基极区; 上方形成P型掺杂的多晶硅的图案化层绝缘马泰-Al的层（66）; 形成N掺杂的多晶硅基因反弹共形地在器件的层（71）; 构图N掺杂多晶硅层，以形成基极接触（71B，71C）基因反弹周围在所述第一器件区和在发射极接触（71C）基因集会由基极接触（52D）在所述第二器件区域所包围的发射极接触; 和至少一次加热装置，以驱动从所述第一和第二器件区域的基极和发射极接触杂质进入器件区域，由此，形成在所述第一器件区和第二器件区的垂直NPN晶体管的垂直型PNP晶体管。

98. 发明公开

EP0417457A3 Method of producing field effect transistor 失效
标题翻译：生产场效应晶体管的方法
公开(公告)号：EP0417457A3
公开(公告)日：1991-07-03
申请号：EP90114790.0
申请日：1990-08-01
申请人： SEIKO INSTRUMENTS INC.
发明人： Saito, Naoto , Aoki, Kenji , Akamine, Tadao , Kojima, Yoshikazu , Kinbara, Masahiko , Takahashi, Kunihiro
IPC分类号： H01L21/225 , H01L21/336 , H01L29/08
CPC分类号： H01L29/66575 , H01L21/2254 , H01L29/66628 , H01L29/66636
摘要： An impurity adsorption layer is selectively formed from a gas containing an impurity on a semiconductor surface. Solid-phase diffusion of the impurity is effected from the impurity adsorption layer into the semiconductor surface to form a source region and a drain region having a sufficiently small resistivity and an ultrashallow PN junction depth, thereby producing a metal-insulator semiconductor field-effect-transistor featuring fast operating speed and reduced dimension.

99. 发明公开

EP0417456A3 Method of producing semiconductor device 失效
标题翻译：生产半导体器件的方法
公开(公告)号：EP0417456A3
公开(公告)日：1991-07-03
申请号：EP90114789.2
申请日：1990-08-01
申请人： SEIKO INSTRUMENTS INC.
发明人： Kamiya, Masaaki, C/o Seiko Instruments Inc. , Aoki, Kenji, C/o Seiko Instruments Inc. , Saito, Naoto, C/o Seiko Instruments Inc.
IPC分类号： H01L21/225 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/2254 , H01L29/6659 , H01L29/78 , Y10S438/974
摘要： An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions of the metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing fast and micro semiconductor devices.

100. 发明公开

EP0434153A1 A method of making a semiconductor device with a npn bipolar transistor 失效
标题翻译： Verfahren zur Herstellung einer Halbleiteranordnung mit einem NPN Bipolartistor。
公开(公告)号：EP0434153A1
公开(公告)日：1991-06-26
申请号：EP90203348.9
申请日：1990-12-17
申请人： Philips Electronics N.V.
发明人： van Schravendijk, Bart
IPC分类号： H01L21/225 , H01L21/265 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/2257
摘要： A method for making a semiconductor device with a bipolar transistor utilizes an amorphous silicon layer as a diffusion source. The layer is successively implanted with boron and arsenic ions. In a single annealing step, dopants are then simultaneously out-diffused from the layer to form both base (34) and emitter (32) regions in an underlying monocrystalline silicon body.
摘要翻译：用双极晶体管制造半导体器件的方法利用非晶硅层作为扩散源。该层依次植入硼和砷离子。在单个退火步骤中，掺杂剂然后同时从该层出来扩散，以形成底层单晶硅体中的基极（34）和发射极（32）。

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