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91. 发明公开

EP0532552A1 TIME BASED SIGNAL DETECTOR 失效
标题翻译： ZEITBASIERTER SIGNALDETEKTOR。
公开(公告)号：EP0532552A1
公开(公告)日：1993-03-24
申请号：EP91910010.0
申请日：1991-05-13
申请人： MOTOROLA, INC.
发明人： LAFLIN, Timothy, C.
IPC分类号： H04B1 , H04L7 , H04W88
CPC分类号： H04L7/0338 , H04W52/0216 , H04W52/0248 , H04W88/026 , Y02D70/122
摘要： A receiver capable of receiving a plurality of signals, wherein more of the signals are received at a peak time than at an off peak time, comprises the method of a first step for determining if the signals are being received by searching in a first search mode and a second step for determining if the signals are not being received by searching in a second search mode. Selection circuitry activates the first step during the peak time and activates the second step during the off peak time. The first and second search modes comprise searching for the signal and searching for noise, respectively.
摘要翻译：一种能够接收多个信号的接收机，其中在高峰时间比在非高峰时间接收更多的信号，包括用于通过在第一搜索模式中搜索来确定是否正在接收信号的第一步骤的方法以及第二步骤，用于通过在第二搜索模式中搜索来确定信号是否未被接收。选择电路在高峰时间激活第一步，并在关闭高峰时间激活第二步。第一和第二搜索模式包括分别搜索信号和搜索噪声。

92. 发明公开

EP0511836A3 Broadband digital phase aligner 失效
标题翻译：宽带数字相位对准器
公开(公告)号：EP0511836A3
公开(公告)日：1992-12-23
申请号：EP92303837.6
申请日：1992-04-29
申请人： MOTOROLA, INC.
发明人： Lowrey, Scott W. , Porter, Jeffrey A.
IPC分类号： H04L7/033
CPC分类号： H04L7/0338 , H04L7/0337
摘要： Automatic dynamic phase alignment of digital data (D), skewed with respect to a local clock, is obtained over a wide range of skew and skew frequencies. The system (50) includes (i) an edge detector (52) containing predetermined delays (e.g., D1, D2, D3), (ii) delay registers (e.g., 72, 76, 84, 86), and (iii) a controller (54) for deciding when un-delayed and delayed data D0, D1, D2, D3 have transitions (102 - 138) which bracket corresponding clock transitions (100, 110, 120, 130) and regulating a subsequent two-stream parallel (e.g.,bi-phase) register-multiplexer (56). The controller (54) selects from the register-multiplexer (56), whichever of in-phase data D or delayed data DD has its transition (102 - 138) spaced away from the clock transition (100, 110, 120, 130) by at least one delay D1, D2, or D3.

93. 发明公开

EP0506136A2 Broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networks 失效
标题翻译： Rundfunk- / SchaltvorrichtungfürRundfunk-Multi-Übertragungenüberungepufferte asynchroneWählvermittlungsnetze。
公开(公告)号：EP0506136A2
公开(公告)日：1992-09-30
申请号：EP92105461.5
申请日：1992-03-30
申请人： International Business Machines Corporation
发明人： Olnowich, Howard Thomas , Lusch, Robert Francis , Jabusch, John David
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L12/1881 , H04L49/101 , H04L49/15 , H04L49/1523 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/40 , H04L49/555 , H04Q11/0066 , H04Q11/0478
摘要： A broadcast/switching apparatus makes input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new asynchronous approach to resolve either broadcast or multi-cast contention among input ports. The broadcast/switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the broadcast/switch requires absolutely no synchronization among any of the input and output ports which interface to the broadcast/switch. The broadcast/switch also incorporates a new accept protocol that enables a positive feedback indication to be returned to the sender of a multi-cast or broadcast operation to inform it that the multi-cast or broadcast transmission was correctly received by all elements involved in the multi-cast or broadcast. In addition, the positive feedback is not affected by elements attached to the broadcast/switch that are not participating in the multi-cast or broadcast, or are disabled elements due to detected failures. The broadcast/switch is completely void of centrally-controlled clocking and any data buffering. Data which traverses the switch encounters only three gate delays -- on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count so that the broadcast/switch design is never gate-limited. Each broadcast/switch port interface requires several parallel data lines plus four control lines.
摘要翻译：广播/交换装置使得输入端口以标准模式从请求的基础上以任何一个输入端口输出到任何一个输出端口，以多播模式从任何一个使用新的异步方法将输入端口同时输入到多个输出端口的固定数量的子集，或者以从任何一个输入端口到所有输出端口的广播模式，以解决输入端口之间的广播或多播竞争。广播/交换机以两个周期的时间自动路由，以相同的高速串行速率通过交换机传输数据。广播/交换机的正常模式在与广播/交换机接口的任何输入和输出端口中绝对不同步。广播/交换机还包括一个新的接受协议，使得能够将正反馈指示返回到多播或广播操作的发送者，以通知它多媒体或广播传输被所有元素正确地接收多播或广播。此外，正反馈不受附加到广播/交换机的不参与多播或广播的元件或由于检测到的故障而被禁用的元件的影响。广播/交换机完全无中央控制的时钟和任何数据缓冲。穿过交换机的数据仅遇到三个门延迟 - 片上接收器，多路复用器和片外驱动器。在芯片上检测和解决争用，但是逻辑实现非常简单，门数很少，因此广播/交换机设计从不限制门限。每个广播/交换机端口接口需要几条并行数据线加上四条控制线。

94. 发明公开

EP0505782A2 Multi-function network 失效
标题翻译： Multifunktionsnetzwerk。
公开(公告)号：EP0505782A2
公开(公告)日：1992-09-30
申请号：EP92103761.0
申请日：1992-03-05
申请人： International Business Machines Corporation
发明人： Olnowich, Howard Thomas , Barker, Thomas Norman , Frasaszek, Peter Anthony , Heidelberger, Philip , Rathi, Bharat Deep , Varma, Anujan Mangala
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L12/1881 , H04L49/101 , H04L49/15 , H04L49/201 , H04L49/205 , H04L49/557 , H04Q11/0066 , H04Q11/0478
摘要： A multi-stage switch architecture for providing for using a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between all N and M devices within the same network. This permits a non-blocked path between 2 devices to be found by "rearrangeability" - the act of trying or searching different alternate paths until a non-blocked connection is established. The rearrangeability architecture disclosed is implemented completely in hardware, and is performed automatically and transparently in relation to the software. A second network function permits the ALTERNATE PATHS to be used selectively for GUARANTEED DELIVERY - a special high priority mode of transfer which will guarantee that the connection will be made to an IDLE device as rapidly as possible, even when "Hot" spots in the network traffic patterns are encountered. In addition, the ALTERNATE PATHS provide another function of providing a more fault tolerant network than provided by state-of-the-art solutions.
As a result of our inventions we provide a single, unidirectional, unbuffered, multi-stage network capable of doing the total network job consisting of multiple functions. The functional complexity provided usually requires several state-of -the-art multi-stage networks to perform the equivalent job. The single network disclosed here allows traffic in both directions, provides for non-blocking via ALTERNATE PATHS and REARRANGEABILITY, incorporates GUARANTEED DELIVERY and FAULT TOLERANCE, and yet is very compact and inexpensive to implement. In addition, the network is modular in nature and permits easy adaptation to any sized system.
摘要翻译：一种多级交换机架构，用于提供多重使用单个交换组件以创建能够执行多种功能的单个网络。所公开网络的一个功能是通过在同一网络内的所有N和M设备之间实现ALTERNATE PATHS来规避多级网络中传统的阻塞问题。这允许通过“可重新排列”找到2个设备之间的非阻塞路径 - 尝试或搜索不同的备用路径，直到建立了非阻塞连接。所公开的可重新布置架构完全在硬件中实现，并且相对于软件自动且透明地执行。第二个网络功能允许ALTERNATE PATHS被选择性地用于保证交付 - 一种特殊的高优先级传输方式，即使在网络中的“热”点也将尽可能快地连接到IDLE设备遇到流量模式。此外，ALTERNATE PATHS还提供另一个提供比最先进解决方案提供的更容错网络的功能。作为我们发明的结果，我们提供了一个单一的，单向的，无缓冲的多级网络，能够完成由多个功能组成的整个网络作业。提供的功能复杂性通常需要几个最先进的多级网络来执行等效的工作。这里公开的单一网络允许双向流量，通过ALTERNATE PATHS和REARRANGEABILITY提供非阻塞，并结合了保证交付和故障保修，但实现起来非常紧凑和便宜。此外，网络本质上是模块化的，并允许轻松适应任何大小的系统。

95. 发明公开

EP0505781A2 Multi-media serial line switching adapter for parallel networks and heterogeneous and homologous computer system 失效
标题翻译： Mehrmedien serielerLinienwählerfürParallelnetzwerke und ein heterogenes homologes Rechnersystem。
公开(公告)号：EP0505781A2
公开(公告)日：1992-09-30
申请号：EP92103748.7
申请日：1992-03-05
申请人： International Business Machines Corporation
发明人： Olnowich, Howard Thomas
IPC分类号： G06F15/16 , H04L29/06
CPC分类号： H04L1/0057 , G06F11/261 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L12/1881 , H04L49/101 , H04L49/1523 , H04L49/201 , H04L49/253 , H04L49/351 , H04L49/357 , H04L69/08 , H04L69/18 , H04Q11/0066 , H04Q11/0478
摘要： A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations. A a parallel electrical switch can efficiently handle either optical or electrical serial data and utilize information via wireless gateways to provide the features required for parallel processing and "farm" approaches, such as low latency, high bandwidth, scalability, fault tolerance, and high reliability. In addition, further flexibility is provided which permits the switching adapter to be personalized to support the any one of a number of standard and proprietary serial protocols. A personalisation PROM specifies the particular serial protocol that each individual adapter is to support. The parallel switching network becomes a flexible media that interconnects and allows different serial protocols to communicate with each other; i.e., any number of different serial protocols can interface with the same parallel switch network. This allows every node of the parallel system to send and receive messages using its own native protocol. However, a node is not restricted to communicating only with others nodes using the same protocol, but it can communicate with any of the other nodes regardless of the serial protocol they use. The switch enables generic networks with heterogeneous and/or homologous nodes as a computer system. It can replace LANs and WANs and provide high speed cluster switching. Applications include parallel processing with existing computers, and features of multiple processor computer system which transfer multi-media information from one or many senders to one or many receivers, useful in teaching and many other applications. The nodes of an asynchronous computer system are connected asynchronously in a non-blocking by search manner with connections for set up at 2 cycles per cascaded node and message transfer continues at maximum media transfer speed.
摘要翻译：通用网络设备包括用于通过交换网络在多个节点之间执行并行或串行通信的串行线路交换设备。一个方面包括使用光或电传输介质来适应与并行交换机接口的标准和专有串行接口。转换的串行数据通过并行交换网路路由到所选择的目的地，接收并转换回串行光或电接口/协议。因此，开关适配器和ALLNODE并行交换网络的组合使得可以将串行消息数据切换并路由到各种目的地。并行电气开关可以有效地处理光或电串行数据，并通过无线网关利用信息来提供并行处理和“农场”方法所需的特性，例如低延迟，高带宽，可扩展性，容错和高可靠性。此外，还提供了进一步的灵活性，其允许将开关适配器个性化以支持多种标准和专有串行协议中的任何一种。个性化PROM指定每个单独适配器要支持的特定串行协议。并行交换网络成为互连并允许不同串行协议相互通信的灵活介质; 即任何数量的不同的串行协议都可以与相同的并行交换网络接口。这允许并行系统的每个节点使用自己的本地协议来发送和接收消息。然而，节点不仅限于使用相同协议与其他节点进行通信，而是可以与任何其他节点进行通信，而不管其使用的串行协议如何。该交换机使具有异构和/或同源节点的通用网络作为计算机系统。它可以替代LAN和WAN，并提供高速集群切换。应用包括与现有计算机的并行处理，以及多处理器计算机系统的特征，其将多媒体信息从一个或多个发送者传送到一个或多个接收机，这在教学和许多其它应用中是有用的。异步计算机系统的节点通过搜索方式以非阻塞方式异步连接，连接以每个级联节点设置为2个周期，并且消息传输以最大的媒体传输速度继续。

96. 发明公开

EP0505780A2 Priority broadcast and multi-cast for unbuffered multi-stage network 失效
标题翻译： Prioritätsrundfunkund Multi-Übertragungfürungepufferte Mehrstufen-Netzwerke。
公开(公告)号：EP0505780A2
公开(公告)日：1992-09-30
申请号：EP92103747.9
申请日：1992-03-05
申请人： International Business Machines Corporation
发明人： Olnowich, Howard Thomas , Barker, Thomas Norman , Kogge, Peter Michael , Vandling III, Gilbert Clyde
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L12/1881 , H04L49/15 , H04L49/1523 , H04L49/201 , H04L49/205 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is a dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new high priority approach to resolve either broadcast or multi-cast contention amongst input ports. The disclosed priority broadcast and multi-cast functions provide a more complex, yet faster and higher powered broadcast and multi-cast function. The disclosed invention permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. In addition, the present invention permits multiple multi-cast operations to occur simultaneously within in the network. This is becoming an increasingly important function for future massively parallel processors consisting of many nodes that can be subdivided into many tasks. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate amongst themselves without involving other nodes that are not in its own subset. The present invention provides a network capable of sustaining many multi-casts simultaneously, thus, providing a very powerful tool for future parallel applications. In accordance with our inventions, we provide hardware circuitry for the detection and correction of deadlock conditions in the multi-stage network. Deadlock conditions are not expected to be usual conditions in the network, but there is a possibility of their occurrence resulting from multiple simultaneous broadcasts or multi-casts colliding within the network in a manner which is not resolvable. The hardware circuitry detects all the different types of deadlock conditions automatically and issues correction indications to the network paths involved. The network deadlock is thereby eliminated, and the two broadcasts or multi-casts involved continue their operation in a rearranged sequence that will not cause deadlock.
摘要翻译：公开了一种双重优先级切换装置，用于使得输入端口以任何一个输入端口至任何一个输出端口的标准模式快速且动态地输出端口连接，以多播模式从任何一个输入端口同时进入多个输出端口的固定数量的子集，或者以广播模式从任何一个输入端口同时传输到所有输出端口，使用新的高优先级方法来解决广播或多播竞争在输入端口之间。所公开的优先广播和多播功能提供了更复杂，更快和更高功率的广播和多播功能。所公开的发明允许在单个交换设备上排队多个广播，其在同步优先级驱动的基础上解决广播争用，允许一个广播在最早的可能时刻和最快的可能速度下跟随另一个广播。此外，本发明允许多个多播操作同时发生在网络内。这对于将来可能被细分为许多任务的许多节点组成的未来的大规模并行处理器正在成为日益重要的功能。多播功能允许分配给相同任务的节点的子集在它们之间通信，而不涉及不在其自己的子集中的其他节点。本发明提供了能够同时维持许多多播的网络，从而为将来的并行应用提供非常强大的工具。根据我们的发明，我们提供用于检测和校正多级网络中的死锁状况的硬件电路。死锁条件不被认为是网络中的通常情况，但是存在由多个同时广播或多播在网络中以不可解决的方式进行冲突的可能性。硬件电路自动检测所有不同类型的死锁状态，并对所涉及的网络路径发出校正指示。因此，网络死锁被消除，并且涉及的两个广播或多播将继续以重新排列的顺序进行操作，这将不会导致死锁。

97. 发明公开

EP0384918A1 Verfahren und Anordnung zum Anpassen eines Taktes an ein plesiochrones Datensignal und zu dessen Abtakten mit dem angepassten Takt 失效
标题翻译：方法和用于调整时钟准同步数据信号配置和其与所述调整的时钟计时。
公开(公告)号：EP0384918A1
公开(公告)日：1990-09-05
申请号：EP89103170.0
申请日：1989-02-23
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Krämer, Horst, Dipl.-Ing. , Klinger, Karlheinz, Dipl.-Ing.
IPC分类号： H04L7/02
CPC分类号： H04L7/0338
摘要： Aus dem Takt (T1) werden über eine Laufzeitkette (3-6) weitere Takte (T2-Tn) derart abzuleiten, daß eine Taktfolge (T1-Tn) mit gleichen Phasenabständen entsteht. Diese Takte (T1 bis Tn) werden in flankengetriggerten D-Flipflops (7-11) vom Datensignal (D1) abgetaktet. Ein Unterschied zwischen den logischen Zuständen an den Q-Ausgängen zweier benachbarter D-Flipflops (7-11) ergibt eine Vorauswahl des am besten angepaßten Taktes. Ausgehend von den Q- und QN-Ausgängen der D-Flipflops (7-11) und den nichtinvertierenden und invertierenden Ausgängen von Verstärkern (12-16) schaltet eine Gatteranordnung (18) einen optimal angepaßten Takt (CLK*) zum Taktausgang (21) durch. Das Datensignal (D1) wird in einem Laufzeitglied (17) um die Zeit verzögert, die die Auswahl des optimal angepaßten Taktes (CLK*) erfordert. Dieser taktet dann im flankengetriggerten D-Flipflop (19) das verzögerte Datensignal (D2) ab.
Die Anordnung ist für einen Einsatz in schnellen Blockvermittlungen mit lokaler oder auch zentraler Taktversorgung geeignet.
摘要翻译：从时钟（T1），进一步的时钟（T2-TN）是通过渡越时间链（3-6）到导出这样做以相同的相位间隔产生的时钟序列（T1-TN）。这些时钟（T1至Tn）从数据信号（D1）在边沿触发的D-触发器（7-11）而得。在两个相邻的D-触发器（7-11）的Q输出端的逻辑状态之间的差产生[OPTI马利angepasst时钟的预选。在D触发器（7-11）和所述非反相和放大器的反相输出端（12-16）的Q和QN输出的基础上，一个门阵列（18）连接到OPTI马利angepasst时钟（CLK <*>）通过对时钟输出（21）。数据信号（D1）在延迟部件（17）由用于OPTI马利angepasst时钟的选择（CLK <*>）所需要的时间延迟。然后，后者钟表在边沿触发的D触发器（19）的延迟的数据信号（D2）。 ... 的装置是适合于在高速块交换系统与本地或中央时钟供给使用。 ... ...

98. 发明公开

EP0383557A1 Network clock synchronisation 失效
标题翻译： Netzwerktakt同步。
公开(公告)号：EP0383557A1
公开(公告)日：1990-08-22
申请号：EP90301540.2
申请日：1990-02-14
申请人： BRITISH TELECOMMUNICATIONS public limited company
发明人： Ballance, John William
IPC分类号： H04B10/20 , H04L7/033
CPC分类号： H04L7/0338 , H04L7/044 , H04L2012/561 , H04L2012/5616 , H04L2012/5652 , H04L2012/5674
摘要： In a network including an exchange 1 having a masterclock 5 and a number of subscriber stations 3 connected to the exchange, the exchange 1 includes a delay line 7 which receives incoming data. Samples are taken from different taps of the delay line 7 and the tap carrying data in phase with the masterclock 5 identified and used to output data.
In a preferred example the network is an optical network carrying data cells.
摘要翻译：在包括具有主时钟5的交换机1和连接到交换机的多个用户站3的网络中，交换机1包括接收输入数据的延迟线7。样本取自延迟线7的不同抽头，并且抽头承载数据与被识别并用于输出数据的主时钟5同相。在优选示例中，网络是携带数据单元的光网络。

99. 发明授权

EP0183875B1 Clocked logic device 失效
标题翻译：时钟逻辑器件
公开(公告)号：EP0183875B1
公开(公告)日：1990-03-14
申请号：EP84115999.9
申请日：1984-12-20
申请人： ADVANTEST CORPORATION
发明人： Misono, Toshiaki
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00234 , H04L7/0338

100. 发明公开

EP0351072A2 Digital phase-locked device and method 失效
标题翻译： Digitale Phasenregeleinrichtung und Verfahren。
公开(公告)号：EP0351072A2
公开(公告)日：1990-01-17
申请号：EP89306120.0
申请日：1989-06-16
申请人： International Business Machines Corporation
发明人： Melrose, Caryn Gallo , Rose, Joe David
IPC分类号： H03L7/081 , H04L7/02 , H04L7/033
CPC分类号： H04L7/0338 , H03L7/0814 , H04L7/0004
摘要： An improved digital phase-locked device and method for synchronising incoming data (8) with a local clock (24) includes registers (12a,12b) which, when alternately triggered during each successive selection cycle, trap the states of waveforms supplied by a delay element string (11). A transition detector (13) detects transitions in these waveforms and provides to a selection means (17, 18, 19) a plurality of outputs, each corresponding directly to a respective clock position. Registers 19a, 19b of the selection means are alternately triggered by clock signals. Selection means 19 provides a window (SW) defining the maximum number of unique clock positions adjacent a then present clock position within which bit patterns are examined for determining whether any of the clock positions then within the window constitutes a valid local clock selection choice. While in a locked mode, if a bit pattern within window (SW) denotes only one local clock selection choice, that clock position is selected and locked as the local clock. If the bit pattern in window (SW) denotes none or more than one local clock selection choice, then unlocking is deferred until at least the next selection cycle. If during the deferral period, the bit pattern denotes only one clock selection choice, that clock position will be selected and locked as the local clock; otherwise unlocking will occur.
摘要翻译：一种用于将输入数据（8）与本地时钟（24）同步的改进的数字锁相装置和方法包括寄存器（12a，12b），当在每个连续选择周期期间交替触发时，捕获由延迟提供的波形的状态元素串（11）。转换检测器（13）检测这些波形中的转换，并向选择装置（17,18,19）提供多个输出，每个输出直接对应于相应的时钟位置。选择装置的寄存器19a，19b由时钟信号交替触发。选择装置19提供一个窗口（SW），其限定与当前时钟位置相邻的最大数目的唯一时钟位置，在该时钟位置内检查位模式，以便确定窗口内的任何一个时钟位置是否构成有效的本地时钟选择选择。在锁定模式下，如果窗口（SW）内的位模式仅表示一个本地时钟选择选择，则选择该时钟位置并将其锁定为本地时钟。如果窗口（SW）中的位模式表示无或多于一个本地时钟选择选择，则解锁延迟至少至少下一个选择周期。如果在延迟期间，位模式仅表示一个时钟选择选择，该时钟位置将被选择并锁定为本地时钟; 否则将会解锁。

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