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91. 发明公开

EP0436753A1 Verfahren zur Herstellung eines selbstjustierten Emitter-Basis-Komplexes 失效
标题翻译：一种用于制造自对准的发射极 - 基极复杂的过程。
公开(公告)号：EP0436753A1
公开(公告)日：1991-07-17
申请号：EP90100320.2
申请日：1990-01-08
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Hoepfner, Achim, Dipl.-Ing. , Tews, Helmut, Dr. Dipl.-Phys. , Zwincknagl, Peter, Dr. Dipl.-Phys.
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L21/28 , Y10S148/01 , Y10S438/951
摘要： Verfahren zur Herstellung eines selbstjustierten Emitter-Basis-Komplexes, bei dem eine Folge von Epitaxieschichten (1), die der optimalen Basis-Emitter-Schichtfolge im rückgeätzten Teil des Heterobipolartransistors entspricht, aufgewachsen, danach die Basisimplantierung (9) unter Verwendung eines Dummy-Emitters (3) als Maske eingebracht wird und unter Verwendung einer den von dem Dummy-Emitter (3) nicht bedeckten Bereich abdeckenden Dielektrikummaske (7) nach Entfernen des Dummy-Emitters (3) in dessen Bereich die Emitterkontaktschichten (8) selektiv aufgewachsen werden und anschließend die Kontaktierung erfolgt.
摘要翻译：一种用于制造自对准的发射极 - 基配合物，其中外延层的序列对应于在异质的蚀刻回部分的最佳基极发射极层序列（1）的过程，长大了，（9）使用虚拟发射极则基本注入（3）被引入作为掩模，利用覆盖介电掩模从伪发射器（3）区域未覆盖（7）在发射极接触层（8）的区域中去除所述伪发射器（3）后有选择地生长，然后的接触。

92. 发明公开

EP0420322A1 Procédé de réalisation d'un circuit semiconducteur intégré incluant un transistor bipolaire à hétérojonction et/ou des résistances enterrées 失效
标题翻译：一种用于生产半导体集成电路，包括一个异质结双极晶体管和/或掩埋电阻过程。
公开(公告)号：EP0420322A1
公开(公告)日：1991-04-03
申请号：EP90202453.8
申请日：1990-09-17
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS S.A.S. , Philips Electronics N.V.
发明人： Villalon, Claudine, Société Civile S.P.I.D.
IPC分类号： H01L21/82 , H01L21/331
CPC分类号： H01L29/66318 , H01L21/28 , H01L21/8252 , Y10S148/011 , Y10S148/072
摘要： L'invention concerne un procédé de réalisation d'un transistor HBT non planaire comprenant d'abord la formation de l'émetteur, la gravure du dispositif autour de l'émetteur jusqu'au niveau de la couche de base, l'ouverture d'une région pour le contact de collecteur, l'émetteur étant protégé, puis la réalisation du contact de base par autoalignement sur l'émetteur et le collecteur. Ce procédé met en oeuvre des étapes d'inversion de profil durant lesquelles on utilise le dépôt successif de deux couches diélectriques de matériaux différents dont la première a une épaisseur uniforme et la seconde une épaisseur non uniforme et qui sont gravées avec des vitesses différentes pour faire apparaître des motifs choisis. L'invention permet en outre de réaliser de manière concomitante des résistances enterrées. Le dispositif obtenu est particulièrement compact et performant et le procédé ne nécessite qu'un nombre d'étapes de masquage très limité et réalisables avec une résolution non critique.
Application : réduction de la surface des circuits intégrés incluant des transistors HBT et des résistances

93. 发明公开

EP0387010A3 Hetero-junction bipolar transistor 失效
标题翻译：异相双极晶体管
公开(公告)号：EP0387010A3
公开(公告)日：1990-10-10
申请号：EP90302391.9
申请日：1990-03-06
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Inada, Masanori , Ryoji, Akira
IPC分类号： H01L29/73 , H01L29/62
CPC分类号： H01L29/66318 , H01L21/28 , H01L29/7371
摘要： An object of the present invention is to suppress the surface recombination over the whole area of the external base of a hetero-junction bipolar transistor (HBT), to keep the current gain large, and to reduce the base contact resistance. The HBT of the invention has, as a surface protective film layer, a p-type semiconductor layer which has the higher portential of the energy conduction band than the base layer on an external base outside the junction between the mesa of the n-type emitter layer and the p-type base layer, and a base electrode thereon. Preferably, it has as a base contact layer a p-type semiconductor layer which shows reduced contact resistance with the base electrode on the surface protective layer comprising a p-type semiconductor layer. More preferabiy, it has a structure wherein a base electrode is formed on the base contact layer in contact with the projection part of the emitter electrode to the base contact layers A method of producing this HBT comprises at least the steps of forming an emitter mask on the portion to be an emitter on a multi-layer structure material having an n-type semiconductor layer for forming a collector, a p-type semiconductor layer or forming a base, and an n-type semiconductor layer for forming an emitter in this order from the substrate, and etching by using the emitter mask to form an emitter mesa and to expose a base layer; epitaxially forming as a surface protective film layer a p-type semiconductor layer which show the higher potential of the energy conduction band than the base layer on the external base outside the junction part between the emitter mesa and the base layer by using the emitter mask; and epitaxially forming a base electrode on the p-type surface protective film layer.

94. 发明公开

EP0300803A3 High-frequency bipolar transistor and its fabrication method 失效
标题翻译：高频双极晶体管及其制造方法
公开(公告)号：EP0300803A3
公开(公告)日：1990-05-16
申请号：EP88306729.0
申请日：1988-07-22
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Ota, Yorito , Inada, Masanori , Yanagihara, Manabu
IPC分类号： H01L29/06 , H01L29/73
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： A bipolar transistor with improved high-frequency performance is invented. The improvement is attained by eliminating a parasitic base-collector capacitance. The invented transistor is constructed upon a semi-insulating substrate, and wherein a region which underlies an extrinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector contact region and the collector region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the substrate. As a result, the transistor has substantially no parasitic base-collector capacitance. Also, a novel method, utilizing a self-align technique which uses a "first mask" for defining a collector contact region and a collector region, a "second mask" for defining an extrinsic base region, and a "third mask" determined by self-alignment using the first and the second mask for defining an emitter region, is disclosed to fabricate the bipolar transistor mentioned above.

95. 发明公开

EP0306258A3 Transistor 失效
标题翻译：晶体管
公开(公告)号：EP0306258A3
公开(公告)日：1989-10-18
申请号：EP88308002.0
申请日：1988-08-30
申请人： AT&T Corp.
发明人： Lunardi, Leda M. , Malik, Roger J.
IPC分类号： H01L29/36 , H01L29/72 , H01L29/10 , H01L29/205 , H01L21/203
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/365 , H01L29/7373
摘要： A transistor (10) is described in which the base region (14) comprises a submonolayer of essentially only dopant atoms. One embodiment is a GaAs/AlGaAs heterojunction bipolar transistor in which the base region comprises a submonolayer of Be atoms. The effective base transit time is negligible in these transistors.

96. 发明授权

EP0125943B1 An indium phosphide-boron phosphide heterojunction bipolar transistor 失效
标题翻译：磷光体 - 磷光体磷光体异相双极晶体管
公开(公告)号：EP0125943B1
公开(公告)日：1987-12-02
申请号：EP84400674.2
申请日：1984-04-05
申请人： ALLIED CORPORATION
发明人： Pande, Krishna Prasad
IPC分类号： H01L29/20 , H01L29/72 , H01L21/36
CPC分类号： H01L29/66318 , H01L29/205 , H01L29/7371

97. 发明公开

EP0240307A2 Bipolar transistor and method of producing the same 失效
标题翻译： Bipolarer晶体管和Sein Herstellungsverfahren。
公开(公告)号：EP0240307A2
公开(公告)日：1987-10-07
申请号：EP87302784.1
申请日：1987-03-31
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Inada, Masanori , Eda, Kazuo , Ota, Yorito , Nakagawa, Atsushi , Yanagihara, Manabu
IPC分类号： H01L29/08 , H01L29/73
CPC分类号： H01L29/66318 , H01L29/0804 , H01L29/41708 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： A dummy emitter (a dummy collector, in inverted type) is formed in the portion corresponding to an emitter (a collector, in inverted type) region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter (collector, in inverted type) region is formed, while the dummy emitter (the dummy collector, in inverted type) is inverted into an emitter (a collector, in inverted type) electrode, thereby forming an emitter (a collector, in inverted type) electrode metal layer to cover the whole upper surface of the emitter (the collector, in inverted type). Using thus formed emitter (collector, in inverted type) electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacently to the emitter (the collector, in inverted type). In other method, on a multilayer structural material, impurities are introduced outside the portion corresponding to the base region of a bipolar transistor in order to insulate, at least, the layer to form the emitter, the layer to form the base, or at most, these layers and the layer to form the collector, and an extension type dummy emitter (dummy collector, in inverted type) extending from the emitter (collector, in inverted type) portion to the insulating region formed by transforming from the semiconductor material to form the emitter (the collector, in inverted type), and using it as mask, the external base region is exposed to form a projection coupling the emitter region and insulating region, and the dummy emitter (the dummy collector, in inverted type) is inverted to transform into an emitter (a collector, in inverted type) electrode metal layer to cover the whole upper surface of the projection.
摘要翻译：在对应于发射器（集电极，倒置型）区域的部分中，在包括用于形成发射极，基极和集电极的层的多层结构材料上形成虚拟发射极（倒置型的虚设集电极），并将其用作掩模，通过蚀刻暴露外部基极区域，并且形成发射极（集电极，倒置型）区域的突起，而虚拟发射极（反相型虚拟集电极）被反转为发射极（集电极，反转型）电极，从而形成发射极（集电极，倒置型）电极金属层，以覆盖发射体（集电极，倒置型）的整个上表面。使用如此形成的发射极（集电极，倒置型）电极金属层，通过自对准，与发射极（集电极，倒置型）相邻形成基极金属层。在其他方法中，在多层结构材料上，杂质被引入到与双极晶体管的基极区域相对应的部分的外部，以便至少使层形成发射极，形成基底的层或至多绝缘层，这些层和形成集电极的层，以及从发射极（集电极，倒置型）部分延伸到通过从半导体材料转变形成的绝缘区域的延伸型虚拟发射极（倒置型的虚设集电极）发射极（集电极，倒立型），并将其用作掩模，外部基极区域暴露以形成耦合发射极区域和绝缘区域的突起，并且虚拟发射极（倒置型的虚设集电极）被反转转换为发射极（集电极，倒置型）电极金属层，以覆盖投影的整个上表面。

98. 发明公开

EP0125943A1 An indium phosphide-boron phosphide heterojunction bipolar transistor 失效
标题翻译：一种双极晶体管，异质结磷化铟磷化硼。
公开(公告)号：EP0125943A1
公开(公告)日：1984-11-21
申请号：EP84400674.2
申请日：1984-04-05
申请人： ALLIED CORPORATION
发明人： Pande, Krishna Prasad
IPC分类号： H01L29/20 , H01L29/72 , H01L21/36
CPC分类号： H01L29/66318 , H01L29/205 , H01L29/7371
摘要： A heterojunction bipolar transistor having an n-type epitaxial indium phosphide collector layer (16) grown on a semi-insulating indium phosphide substrate (18) with an n+ buried layer (20), a p-type indium phosphide base (26) and an epitaxpial, n-type boron phosphide wide gap emitter (24). The p- type base region (26) is formed by ion implantation of magnesium ions into the collector layer (16). The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2eV) and indium phosphide (1.34eV) permit operation up to 350°C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.

99. 发明授权

EP1636855B1 GALLIUM ARSENIDE HBT AND METHOD FOR ITS FABRICATION 有权
标题翻译：砷化镓HBT及其制造方法
公开(公告)号：EP1636855B1
公开(公告)日：2016-12-14
申请号：EP04709899.1
申请日：2004-02-10
申请人： Skyworks Solutions, Inc.
发明人： ZAMPARDI, Peter, J. , CHOI, Kevin , RUSHING, Lance, G.
IPC分类号： H01L31/0328
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/2003 , H01L29/7371

100. 发明授权

EP2076919B1 Method of forming local collector implant structure for heterojunction bipolar transistors 有权
标题翻译：一种用于产生一本地集电极植入结构为异质结双极晶体管的过程
公开(公告)号：EP2076919B1
公开(公告)日：2012-08-29
申请号：EP07820265.2
申请日：2007-09-17
申请人： International Business Machines Corporation
发明人： PAGETTE, Francois
IPC分类号： H01L21/331 , H01L29/737 , H01L29/08
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/66242 , H01L29/7371 , H01L29/7378

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