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91. 发明公开

EP2646921A2 EFFICIENT CACHE MANAGEMENT 审中-公开
标题翻译：高效的高速缓存内存管理
公开(公告)号：EP2646921A2
公开(公告)日：2013-10-09
申请号：EP11845174.9
申请日：2011-11-22
申请人： Microsoft Corporation
发明人： HSIEH, Bor-Ming , ROGERS, Andrew M.
IPC分类号： G06F12/08
CPC分类号： G06F12/023 , G06F12/0871 , G06F2212/1044 , G06F2212/2515 , G06F2212/601
摘要： A method of managing memory of a computing device includes providing a first memory that can be allocated as cache memory or that can be used by a computing device component. A first memory segment can be allocated as cache memory in response to a cache miss. Cache size can be dynamically increased by allocating additional first memory segments as cache memory in response to subsequent cache misses. Cache memory size can be dynamically decreased by reallocating first memory cache segments for use by computing device components. The cache memory can be a cache for a second memory accessible to the computing device. The computing device can be a mobile device. The first memory can be an embedded memory and the second memory can comprise embedded, removable or external memory, or any combination thereof. The maximum size of the cache memory scales with the size of the first memory.

92. 发明公开

EP2612249A1 METHOD AND SYSTEM FOR REMOVING CACHE BLOCKS 有权
标题翻译： VERFAHREN UND SYSTEM ZUR ENTFERNUNG VONZWISCHENSPEICHERBLÖCKEN
公开(公告)号：EP2612249A1
公开(公告)日：2013-07-10
申请号：EP11758007.6
申请日：2011-08-31
申请人： Oracle International Corporation
发明人： SWART, Garret, Frederick , VENGEROV, David
IPC分类号： G06F12/12
CPC分类号： G06F12/0888 , G06F12/0871 , G06F12/121 , G06F12/123 , G06F2212/461 , G06F2212/465
摘要： A method of inserting cache blocks into a cache queue includes detecting a first cache miss for the cache queue, identifying a storage block receiving an access in response to the cache miss, calculating a first estimated cache miss cost for a first storage container that includes the storage block, calculating an insertion probability for the first storage container based on a mathematical formula of the first estimated cache miss cost, randomly selecting an insertion probability number from a uniform distribution, and inserting, in response to the insertion probability exceeding the insertion probability number, a new cache block corresponding to the storage block into the cache queue.
摘要翻译：将高速缓存块插入高速缓存队列的方法包括：计算高速缓存队列（1002）内的高速缓存块的估计高速缓存未命中的成本，从高速缓存队列中驱逐高速缓存块，插入对应于高速缓存块的存储块的条目变成与缓存队列相对应的影子列表，检测引用存储块（1000）的缓存队列的高速缓存未命中，访问影子列表内的条目，计算估计的高速缓存未命中成本阈值，并响应于所估计的高速缓存插入错过成本超过估计的高速缓存未命中成本阈值，对应于存储块的新的高速缓存块进入高速缓存队列（1006）。

93. 发明公开

EP2438742A1 METHOD AND NODE FOR DISTRIBUTING ELECTRONIC CONTENT IN A CONTENT DISTRIBUTION NETWORK 有权
标题翻译：方法和节点，在内容分发网络中分发电子内容
公开(公告)号：EP2438742A1
公开(公告)日：2012-04-11
申请号：EP09845607.2
申请日：2009-06-03
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： LARS-ÖRJAN, Kling , KJELL, Nyström , JOHANSSON, Thomas , HELLKVIST, Stefan , PUTHALATH, Hareesh
IPC分类号： H04L29/08
CPC分类号： H04L67/06 , G06F12/0871 , G06F12/0888 , G06F2212/263 , G06F2212/284 , H04L67/2842 , H04L67/2852
摘要： The present invention relates to a method and node for efficiently distributing electronic content in a content distribution network (CDN) comprising a plurality of cache nodes. The method defines a virtual node logically representing a set of cache nodes. The set of cache nodes is in turn defined based on an internal communication cost between the cache nodes. In each of the cache nodes represented by the virtual node statistics regarding content requests is collected, and based on this statistics it is determined whether specific content is to be cached in the virtual node or not. If it is determined to cache specific content in the virtual node, the specific content may be caused to be cached in one or more of the cache nodes represented by the virtual node.

94. 发明公开

EP2177985A2 Embedded scale-out aggregator for storage array controllers 有权转让
标题翻译： Eingebetteter Scale-Out SammlerfürSpeichermatrix-Steuergeräten
公开(公告)号：EP2177985A2
公开(公告)日：2010-04-21
申请号：EP09251775.4
申请日：2009-07-10
申请人： LSI Logic Corporation
发明人： Balasubramanian, Sridhar , Hetrick, William , Delaney, William P.
IPC分类号： G06F3/06
CPC分类号： G06F3/0631 , G06F3/0605 , G06F3/0667 , G06F3/067 , G06F3/0689 , G06F12/0871 , G06F12/0873 , G06F2212/263 , H04L67/1097
摘要： Methods and systems for dynamic storage tiering may comprise: discovering one or more remote virtual drives associated with one or more remote storage arrays; advertising one or more local virtual drives associated with a local storage array; receiving one or more lO requests from a client addressed to one or more remote virtual drives associated with one or more remote storage arrays; transmitting one or more command descriptor block (CDB) requests to one or more remote storage arrays associated with the one or more virtual drives to allocate local cache space and transmitting the one or more lO requests to the one or more remote storage arrays via Remote Direct Memory Access (RDMA).
摘要翻译：用于动态存储分层的方法和系统可以包括：发现与一个或多个远程存储阵列相关联的一个或多个远程虚拟驱动器; 发布与本地存储阵列相关联的一个或多个本地虚拟驱动器; 接收来自与一个或多个远程存储阵列相关联的一个或多个远程虚拟驱动器的客户端的一个或多个IO请求; 将一个或多个命令描述符块（CDB）请求发送到与所述一个或多个虚拟驱动器相关联的一个或多个远程存储阵列以分配本地高速缓存空间，并且经由远程直接将所述一个或多个IO请求发送到所述一个或多个远程存储阵列内存访问（RDMA）。

95. 发明公开

EP1826675A3 Storage apparatus and mapping information recovering method for the storage apparatus 审中-公开
标题翻译：存储装置和恢复映射信息存储装置的方法
公开(公告)号：EP1826675A3
公开(公告)日：2008-08-13
申请号：EP07102661.1
申请日：2007-02-19
申请人： SAMSUNG ELECTRONICS CO., LTD. , SAMSUNG ELECTRONICS CO., LTD.
发明人： Shin, Dong-kun , Kim, Jang-hwan , Kim, Jeong-eun
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0871 , G06F11/1441 , G06F12/0246 , G06F2212/222
摘要： A storage apparatus using a nonvolatile memory as a cache and a mapping information recovering method for the storage apparatus are provided. The storage apparatus includes a mapping information storage module which stores in the nonvolatile memory mapping information of the nonvolatile memory and a first physical block address allocated when the mapping information is stored; a scan module which scans the first physical block address through a second physical block address allocated currently; and a mapping information recovery module which recovers the mapping information between the first physical block address and the second physical block address based on a result of the scan by the scan module.

96. 发明授权

EP1074916B1 Hardware mechanism for managing cache structures in a data storage system 有权
标题翻译：用于管理数据存储系统中高速缓存的结构硬件结构
公开(公告)号：EP1074916B1
公开(公告)日：2007-06-13
申请号：EP00305591.0
申请日：2000-07-03
申请人： LSI Logic Corporation
发明人： DeKoning, Rodeny , Gates, Dennis E. , Kloeppner, John R.
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0871

97. 发明公开

EP1562123A1 Storage subsystem and storage subsystem control method 审中-公开
标题翻译： Speicheruntersystem和SteuerverfahrenfürSpeicheruntersystem
公开(公告)号：EP1562123A1
公开(公告)日：2005-08-10
申请号：EP04255715.7
申请日：2004-09-20
申请人： Hitachi, Ltd.
发明人： Hoshino, Sachiko, Hitachi Ltd., IP Group , Sakaguchi, Takashi, Hitachi Ltd., IP Group , Nagasoe, Yasuyuki, Hitachi Ltd., IP Group , Sugino, Shoji, Hitachi Ltd., IP Group
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0601 , G06F12/0866 , G06F12/0871 , G06F2003/0697 , G06F2212/282 , G06F2212/311 , G06F2212/312 , G06F2212/6042 , Y10S707/99943
摘要： The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions.
A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be used by partitioning the cache region of a cache memory. Management information required to manage the data stored in the cache memory is allocated to each CLPR in accordance with the attribute of the segment or slot. The clean queue and clean counter, which manage the segments in a clean state, are provided in each CLPR. The dirty queue and dirty counter are used jointly by all the CLPR. The free queue, classification queue, and BIND queue are applied jointly to all the CLPR, only the counters being provided in each CLPR.
摘要翻译：本发明为每个用户分配存储子系统的高速缓存区域，并且防止用户专用区域之间的干扰。可以在存储子系统内建立多个CLPR。 CLPR是可以通过对高速缓冲存储器的高速缓存区域进行分区来使用的用户专用区域。管理存储在高速缓冲存储器中的数据所需的管理信息根据段或时隙的属性分配给每个CLPR。在每个CLPR中提供清洁队列和清洁计数器，它们管理清洁状态下的段。脏排队和脏计数器由所有CLPR联合使用。空闲队列，分类队列和BIND队列联合应用于所有CLPR，只有每个CLPR中提供的计数器。

98. 发明公开

EP1199637A2 Disk controller comprising cache memory and method of controlling the cache 审中-公开
标题翻译： Festplattensteuerung mit Cachespeicher und Verfahren zur Steuerung des Cachespeichers
公开(公告)号：EP1199637A2
公开(公告)日：2002-04-24
申请号：EP01104056.5
申请日：2001-02-20
申请人： Hitachi, Ltd.
发明人： Kanai, Hiroki, Hitachi Ltd. Intel. Property Group , Fujimoto, Kazuhisa, Hitachi Ltd. Int.Prop.Group , Fujibayashi, Akira, Hitachi Ltd. Int.Prop.Group
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F12/0815 , G06F2212/284 , G06F2212/312
摘要： To execute cache data identity control between disk controllers in plural disk controllers provided with each cache. To prevent a trouble from being propagated to another disk controller even if the trouble occurs in a specific disk controller. The identity control of data is executed via a communication means between disk controllers. In case update access from a host is received, data in a cache memory of a disk controller that controls at least a data storage drive is updated. It is desirable that a cache area is divided into an area for a drive controlled by the disk controller and an area for a drive controlled by another disk controller and is used.
摘要翻译：在每个缓存提供的多个磁盘控制器中的磁盘控制器之间执行缓存数据标识控制。即使在特定的磁盘控制器中发生故障，也可以防止传播到另一个磁盘控制器的故障。通过磁盘控制器之间的通信装置执行数据的身份控制。如果接收到来自主机的更新访问，则更新至少控制数据存储驱动器的磁盘控制器的高速缓冲存储器中的数据。希望将高速缓存区域划分为由盘控制器控制的驱动器的区域和由另一个盘控制器控制的驱动区域。

99. 发明公开

EP0389151A3 System and method for partitioned cache memory management 失效
标题翻译：分区式高速缓存记忆管理
公开(公告)号：EP0389151A3
公开(公告)日：1992-06-03
申请号：EP90302516.1
申请日：1990-03-08
申请人： International Business Machines Corporation
发明人： Mattson, Richard Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0862 , G06F12/0871 , G06F12/0873 , G06F12/0897 , G06F12/128 , G06F2212/282 , G06F2212/311
摘要： Improved performance of the storage system cache memory can be obtained by using a partitioned cache, in which storage data is classified into k categories using a pre-specified scheme of classification, and the cache is partitioned into a global sub-cache and k local sub-caches. When the data is required by the processor, data can be staged from the storage device, or the local sub-caches, to the global sub-cache, with data belonging to one of the categories being pushed from the global sub-cache to a corresponding one of the sub-caches, and additionally pushing data from the sub-caches into the storage device.

100. 发明公开

EP0342846A3 Data protection system in a data processing system 失效
标题翻译：数据处理系统中的数据保护系统
公开(公告)号：EP0342846A3
公开(公告)日：1990-08-22
申请号：EP89304682.1
申请日：1989-05-09
申请人： FUJITSU LIMITED
发明人： Shimoi, Hiroyuki Shirasakahausu 102
IPC分类号： G06F1/00
CPC分类号： G06F11/0754 , G06F1/30 , G06F12/0868 , G06F12/0871 , G06F2212/1032 , G06F2212/312 , G11C5/141 , G11C7/22
摘要： A data protection system for protecting the data stored in a memory (10) in a data processing system having at least a channel system, a device controller (2) and an external storage device (6), includes: a memory (10) provided in the device controller and supplied to a power source voltage from a power source (1), and temporarily storing a data to be transferred; a battery (12) connected to the power source (11) and the memory (10), and charged by the power source (11) when the power source (11) is normal, and supplying a battery voltage to the memory (10) when the power source is accidentally interrupted. The data protection system also includes a first voltage check circuit (13) connected to the battery (12) which compares the battery voltage with a first reference voltage and generates a battery error signal when the battery voltage is lower than the first reference voltage and, a second voltage check circuit (14) connected to the battery (12), which compares the battery voltage with a second reference voltage and generates a battery charging signal when the battery voltage lies between the first reference voltage and the second reference voltage. The data protection system also includes a control circuit (2) for selectively determining two modes, one mode being a write-back mode for transferring the data from the memory to the external storage device after the data is stored in the memory, and the other being a write-through mode for directly transferring the data from the channel system to the external storage device (6) not through the memory (10) when the battery error signal and/or the battery charging signal is input to it.

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