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1. 发明授权

US06930324B2 Device architecture and process for improved vertical memory arrays 失效
标题翻译：用于改进垂直存储器阵列的器件架构和过程
公开(公告)号：US06930324B2
公开(公告)日：2005-08-16
申请号：US10748332
申请日：2003-12-31
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schloesser , Juergen Lindolf
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schloesser , Juergen Lindolf
IPC分类号： G11C29/02 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L27/108 , H10L23/58
CPC分类号： H01L27/10882 , G11C29/02 , G11C29/025 , G11C2029/5002 , H01L22/34 , H01L27/0207 , H01L27/10841 , H01L27/10885 , H01L27/10891 , Y10S257/908
摘要： An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.
摘要翻译：公开了一种用于集成电路的阵列处理诊断测试结构，该集成电路包括由垂直FET存储单元存取晶体管组成的晶体管阵列，其形成为在电路的横向方向上平行延伸的活动腹板形式的衬底的深度。阵列测试结构中的存储单元存储电容器形成在形成垂直FET晶体管的有源平板的这些部分的端面上的深沟槽中。字线沿着幅材布置并且沿阵列的平行相交的位线布置，其外侧和两个相互相对的边缘上设置有第一和第二字线梳。字线梳被偏移并交替连接到不同的字线。此外，在晶体管阵列的另外两个相对的边缘上形成第一和第二位线梳，该第二和第二位线梳被相互偏置并且各自连接到不同的位线。测试结构为垂直FET晶体管的栅极氧化物，深沟槽中的电容电介质，字线之间的电容测量以及字线和其他电路层之间的电容测量提供了便利的方法，以及作为位线之间以及位线和其他电路层之间的电容测量，从而有助于诊断在生产过程中产生的可能的故障源。

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