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1. 发明授权

US06930324B2 Device architecture and process for improved vertical memory arrays 失效
标题翻译：用于改进垂直存储器阵列的器件架构和过程
公开(公告)号：US06930324B2
公开(公告)日：2005-08-16
申请号：US10748332
申请日：2003-12-31
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schloesser , Juergen Lindolf
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schloesser , Juergen Lindolf
IPC分类号： G11C29/02 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L27/108 , H10L23/58
CPC分类号： H01L27/10882 , G11C29/02 , G11C29/025 , G11C2029/5002 , H01L22/34 , H01L27/0207 , H01L27/10841 , H01L27/10885 , H01L27/10891 , Y10S257/908
摘要： An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.
摘要翻译：公开了一种用于集成电路的阵列处理诊断测试结构，该集成电路包括由垂直FET存储单元存取晶体管组成的晶体管阵列，其形成为在电路的横向方向上平行延伸的活动腹板形式的衬底的深度。阵列测试结构中的存储单元存储电容器形成在形成垂直FET晶体管的有源平板的这些部分的端面上的深沟槽中。字线沿着幅材布置并且沿阵列的平行相交的位线布置，其外侧和两个相互相对的边缘上设置有第一和第二字线梳。字线梳被偏移并交替连接到不同的字线。此外，在晶体管阵列的另外两个相对的边缘上形成第一和第二位线梳，该第二和第二位线梳被相互偏置并且各自连接到不同的位线。测试结构为垂直FET晶体管的栅极氧化物，深沟槽中的电容电介质，字线之间的电容测量以及字线和其他电路层之间的电容测量提供了便利的方法，以及作为位线之间以及位线和其他电路层之间的电容测量，从而有助于诊断在生产过程中产生的可能的故障源。

2. 发明授权

US06930325B2 Test structure for improved vertical memory arrays 失效
标题翻译：用于改进垂直存储器阵列的测试结构
公开(公告)号：US06930325B2
公开(公告)日：2005-08-16
申请号：US10766902
申请日：2004-01-30
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
IPC分类号： G11C29/50 , H01L23/58
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/50 , G11C2029/5006
摘要： An integrated circuit arrangement that has an integrated test structure is provided. The integrated circuit arrangement includes a transistor array having vertical FET selection transistors electrically coupled to storage capacitors of an assigned memory cell array, the storage capacitors being formed vertically into the depth of a substrate in deep trenches. The test structure may enable a plurality of vertical FET selection transistors by a conductive electrode material embedded in an extended deep trench. With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.
摘要翻译：提供了具有集成测试结构的集成电路装置。集成电路装置包括具有电耦合到分配的存储单元阵列的存储电容器的垂直FET选择晶体管的晶体管阵列，所述存储电容器垂直形成在深沟槽中的衬底的深度。测试结构可以通过嵌入在延伸的深沟槽中的导电电极材料来实现多个垂直FET选择晶体管。利用这种测试结构，可以评估不同半导体结处以及集成电路装置的不同部分之间的漏电流和电容的特性值，并且还执行可靠性压力测试。

3. 发明申请

US20050040398A1 Test structure for improved vertical memory arrays 失效
标题翻译：用于改进垂直存储器阵列的测试结构
公开(公告)号：US20050040398A1
公开(公告)日：2005-02-24
申请号：US10766902
申请日：2004-01-30
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Juergen Lindolf , Till Schloesser , Bernd Goebel
IPC分类号： G11C29/50 , H01L23/58
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/50 , G11C2029/5006
摘要： An integrated circuit arrangement which has vertical FET selection transistors and storage capacitors in each case of a transistor array and of an assigned memory cell array, said storage capacitors being formed vertically into the depth of a substrate in deep trenches a test structure is integrated, which enables a plurality of vertical FET selection transistors with one another by a conductive electrode material embedded in an extended deep trench With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.
摘要翻译：一种在晶体管阵列和分配的存储单元阵列的每种情况下具有垂直FET选择晶体管和存储电容器的集成电路装置，所述存储电容器垂直形成在深沟槽中的衬底的深度，测试结构被集成，通过嵌入在扩展深沟槽中的导电电极材料使得多个垂直FET选择晶体管彼此具有这种类型的测试结构，可以评估不同半导体结处的漏电流和电容的特性值，以及不同的集成电路布置的部分以及执行可靠性压力测试。

4. 发明授权

US06838724B2 Transistor array and semiconductor memory configuration fabricated with the transistor array 有权
标题翻译：晶体管阵列和晶体管阵列制造的半导体存储器配置
公开(公告)号：US06838724B2
公开(公告)日：2005-01-04
申请号：US10718310
申请日：2003-11-20
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schlösser , Jürgen Lindolf
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schlösser , Jürgen Lindolf
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10841 , H01L27/10891 , H01L29/945
摘要： A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.
摘要翻译：晶体管阵列具有连接到存储单元阵列的存储电容器的垂直FET晶体管。晶体管的形成字线的栅电极条位于相互平行运行的有源网的两侧，并通过字线或CS触点连接到叠加的金属平面。为了将这些字线触点与晶体管阵列和单元阵列的其它元件绝缘，字线触点位于被引入幅材的深沟槽中。

5. 发明授权

US06897077B2 Test structure for determining a short circuit between trench capacitors in a memory cell array 失效
标题翻译：用于确定存储单元阵列中的沟槽电容器之间的短路的测试结构
公开(公告)号：US06897077B2
公开(公告)日：2005-05-24
申请号：US10675494
申请日：2003-09-30
申请人： Andreas Felber , Valentin Rosskopf
发明人： Andreas Felber , Valentin Rosskopf
IPC分类号： H01L23/544 , H01L21/66 , G01R31/26
CPC分类号： H01L22/34
摘要： A test structure allows determining a short circuit between trench capacitors in a memory cell array in which the trench capacitors are arranged in matrix form. The test structure has, in two rows of trench capacitors, a connection of the trench capacitors of each row by tunnel structures and/or bridge structures. A contact area for contact connection is provided at each end section of a trench capacitor row.
摘要翻译：测试结构允许确定其中沟槽电容器以矩阵形式布置的存储单元阵列中的沟槽电容器之间的短路。测试结构在两排沟槽电容器中具有每行的沟槽电容器与隧道结构和/或桥结构的连接。在沟槽电容器行的每个端部设置用于接触连接的接触区域。

6. 发明申请

US20050051765A1 Test structure for a single-sided buried strap DRAM memory cell array 有权
标题翻译：单面埋地带DRAM存储单元阵列的测试结构
公开(公告)号：US20050051765A1
公开(公告)日：2005-03-10
申请号：US10933497
申请日：2004-09-03
申请人： Valentin Rosskopf , Susanne Lachenmann , Sibina Sukman-Prahofer , Andreas Felber
发明人： Valentin Rosskopf , Susanne Lachenmann , Sibina Sukman-Prahofer , Andreas Felber
IPC分类号： G11C29/00 , G11C29/50 , H01L21/8242 , H01L23/544 , H01L31/0328
CPC分类号： H01L27/10873 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L2924/0002 , Y10S257/905 , Y10S257/908 , H01L2924/00
摘要： A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.
摘要翻译：用于确定基于单面掩埋带概念构造的矩阵状单元阵列中的存储单元的电特性的测试结构具有在两个相邻存储单元中的存储电容器中的内部电极之间的连接该行的有源区为了产生串联电路。第一存储单元中的第一选择晶体管和第一存储电容器以及第二存储单元中的第二选择晶体管和第二存储电容器，第一和第二选择晶体管的有源区不连接在第一和第二选择晶体管之间通过接触式位线。

7. 发明授权

US06853000B2 Test structure for determining a doping region of an electrode connection between a trench capacitor and a selection transistor in a memory cell array 失效
标题翻译：用于确定存储单元阵列中的沟槽电容器和选择晶体管之间的电极连接的掺杂区域的测试结构
公开(公告)号：US06853000B2
公开(公告)日：2005-02-08
申请号：US10675051
申请日：2003-09-30
申请人： Andreas Felber , Valentin Rosskopf
发明人： Andreas Felber , Valentin Rosskopf
IPC分类号： G11C29/50 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L29/72
CPC分类号： H01L27/10867 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a trench capacitor to an associated selection transistor. The test structure has an electrical contact with a predetermined contact area disposed between a regular matrix configuration of four trench capacitors.
摘要翻译：用于存储单元阵列的测试结构确定电极连接的掺杂区域，其在存储单元中将沟槽电容器的内部电容器电极连接到相关联的选择晶体管。测试结构具有与设置在四个沟槽电容器的规则矩阵配置之间的预定接触区域的电接触。

8. 发明授权

US07205567B2 Semiconductor product having a semiconductor substrate and a test structure and method 失效
标题翻译：具有半导体衬底和测试结构和方法的半导体产品
公开(公告)号：US07205567B2
公开(公告)日：2007-04-17
申请号：US11336384
申请日：2006-01-20
申请人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.
摘要翻译：具有测试结构的半导体产品，其中公开了通过具有互连的掺杂剂扩散区将接触连接短路到与沟槽电容器的内部电容器电极连接的晶体管的源极/漏极区域。公开了用于进行电气测量的方法，以确定掺杂剂扩散区域的非反应电阻，即所谓的“掩埋带”，而测量结果不被晶体管通道的非反应电阻破坏。根据具有电容器电极的多个电连接的本发明的一个实施例，静电流也可以通过掩埋带和电容器电极进行。公开了使得可以在半导体晶片电阻测量的新颖测试结构下执行，其不能在存储器单元阵列本身的存储器单元处执行。

9. 发明申请

US20060175647A1 Semiconductor product having a semiconductor substrate and a test structure and method 失效
标题翻译：具有半导体衬底和测试结构和方法的半导体产品
公开(公告)号：US20060175647A1
公开(公告)日：2006-08-10
申请号：US11336384
申请日：2006-01-20
申请人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
发明人： Andreas Felber , Susanne Lachenmann , Valentin Rosskopf , Sibina Sukman-Praehofer
IPC分类号： H01L29/94
CPC分类号： H01L22/34 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.
摘要翻译：具有测试结构的半导体产品，其中公开了通过具有互连的掺杂剂扩散区将接触连接短路到与沟槽电容器的内部电容器电极连接的晶体管的源极/漏极区域。公开了用于进行电气测量的方法，以确定掺杂剂扩散区域的非反应电阻，即所谓的“掩埋带”，而测量结果不被晶体管通道的非反应电阻破坏。根据具有电容器电极的多个电连接的本发明的一个实施例，静电流也可以通过掩埋带和电容器电极进行。公开了使得可以在半导体晶片电阻测量的新颖测试结构下执行，其不能在存储器单元阵列本身的存储器单元处执行。

10. 发明授权

US06878965B2 Test structure for determining a region of a deep trench outdiffusion in a memory cell array 失效
标题翻译：用于确定存储单元阵列中的深槽扩散区域的测试结构
公开(公告)号：US06878965B2
公开(公告)日：2005-04-12
申请号：US10675493
申请日：2003-09-30
申请人： Andreas Felber , Valentin Rosskopf
发明人： Andreas Felber , Valentin Rosskopf
IPC分类号： H01L21/8242 , H01L23/544 , H01L29/10
CPC分类号： H01L27/1087 , H01L22/34
摘要： A test structure for determining a doping region of an outer capacitor electrode of a trench capacitor in a memory cell array. The trench capacitors of the memory cell array are arranged in matrix form. The test structure has two parallel rows of trench capacitors. The outer capacitor electrode of each row of trench capacitors is electrically connected to one another and the basic area of at least one trench capacitor of each row is lengthened on the side facing the other row in such a way that the two trench capacitors overlap in a direction transverse to their extent.
摘要翻译：一种用于确定存储单元阵列中的沟槽电容器的外部电容器电极的掺杂区域的测试结构。存储单元阵列的沟槽电容器以矩阵形式布置。测试结构具有两排平行的沟槽电容器。每排沟槽电容器的外部电容电极彼此电连接，并且每行的至少一个沟槽电容器的基本区域在面向另一行的一侧被延长，使得两个沟槽电容器在一个方向横向于其程度。

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