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1. 发明授权

US06836295B1 Audio to video timing measurement for MPEG type television systems 失效
标题翻译：用于MPEG类型电视系统的音频到视频定时测量
公开(公告)号：US06836295B1
公开(公告)日：2004-12-28
申请号：US09545529
申请日：2000-04-07
申请人： J. Carl Cooper
发明人： J. Carl Cooper
IPC分类号： H04N9475
CPC分类号： H04N5/067 , H04N5/06 , H04N5/073 , H04N21/4307 , H04S5/005
摘要： An invention for measuring, maintaining and correcting synchronization between signals which suffer varying relative delays during transmission and/or storage is shown. The preferred embodiment of the invention finds particular use in measuring the relative delay between multiple audio signals and an associated video signal of a television type program which is compressed via MPEG or other compression for a transmission and/or storage system. The invention marks the video signal at a time when a particular event in the associated audio occurs. The mark is carried with the video throughout the video processing. After processing the same event in the audio is again identified, the mark in the video identified, the two being compared to determine the timing difference therebetween.
摘要翻译：示出了用于测量，维持和校正在传输和/或存储期间遭受变化的相对延迟的信号之间的同步的发明。本发明的优选实施例特别用于测量多个音频信号与通过用于传输和/或存储系统的MPEG或其它压缩压缩的电视节目的相关视频信号之间的相对延迟。当相关音频中的特定事件发生时，本发明标记视频信号。在整个视频处理过程中，标记与视频一起携带。在处理相同事件之后，再次识别出音频中的标识符，将视频中的标记进行比较，确定其间的时间差。

2. 发明授权

US06583821B1 Synchronizing apparatus for a compressed audio/video signal receiver 有权
标题翻译：用于压缩音频/视频信号接收机的同步装置
公开(公告)号：US06583821B1
公开(公告)日：2003-06-24
申请号：US09358070
申请日：1999-07-21
申请人： Franck Michel Durand
发明人： Franck Michel Durand
IPC分类号： H04N9475
CPC分类号： H04N21/4396 , H04N21/2368 , H04N21/4305 , H04N21/4341
摘要： A compressed audio/video, includes circuitry to measure the relative synchronization of decompressed audio and video signals. If audio and video signal synchronization is within a first range of values, synchronization circuitry within the receiver will attempt to appropriately time align the signals. Alternatively, if actual synchronization exceeds the first range, attempts to synchronize the signals are suspended and non-synchronized decompressed audio and video signals are provided.
摘要翻译：压缩音频/视频包括用于测量解压缩的音频和视频信号的相对同步的电路。如果音频和视频信号同步在第一范围内，则接收机内的同步电路将尝试适当地对准信号。或者，如果实际同步超过第一范围，则暂停同步信号的尝试，并且提供非同步解压缩的音频和视频信号。

3. 发明授权

US06356312B1 MPEG decoder and decoding control method for handling system clock discontinuity 有权
标题翻译：用于处理系统时钟不连续的MPEG解码器和解码控制方法
公开(公告)号：US06356312B1
公开(公告)日：2002-03-12
申请号：US09217203
申请日：1998-12-22
申请人： Hwa Young Lyu
发明人： Hwa Young Lyu
IPC分类号： H04N9475
CPC分类号： H04N21/4305 , H04N5/04 , H04N5/4401 , H04N21/4307 , H04N21/4341
摘要： An apparatus and method for MPEG decoding are disclosed which control decoding without reference to the system time clock for a predetermined time period during a discontinuity of system time clock. Thus, an error caused by inconsistency between the system time clock and the time stamp due to delay of the video buffer is eliminated, thereby allowing normal decoding with A/V lip-synchronization.
摘要翻译：公开了一种用于MPEG解码的装置和方法，其在系统时钟的不连续性期间，在不参考系统时钟的情况下控制解码达预定时间段的解码。因此，消除了由于视频缓冲器的延迟而导致的系统时钟和时间戳之间的不一致的错误，从而允许通过A / V口唇同步的正常解码。

4. 发明授权

US06323909B1 Method and apparatus for transmitting high definition television programming using a digital satellite system transport and MPEG-2 packetized elementary streams (PES) 有权
标题翻译：使用数字卫星系统传输和MPEG-2分组化基本流（PES）传输高清晰度电视节目的方法和装置
公开(公告)号：US06323909B1
公开(公告)日：2001-11-27
申请号：US09181412
申请日：1998-10-28
申请人： James A. Michener , Robert H. Plummer , Chao-Kung Yang
发明人： James A. Michener , Robert H. Plummer , Chao-Kung Yang
IPC分类号： H04N9475
CPC分类号： H04N21/235 , H04N7/52 , H04N21/434 , H04N21/435
摘要： A system and method for distributing high definition television (HDTV) and standard definition television (SDTV) signals via satellite is disclosed. At the transmission station an MPEG-2 video encoder compresses a video signal and a digital encoder encodes an audio signal. The compressed video and the encoded audio are coupled to PES packetizers, which generate video and audio packetized elementary data streams having PES headers and PES payloads. Within each PES header is a presentation time stamp (PTS), which is representative of the time at which the payload is to be displayed to the user. The packetized elementary data streams are multiplexed together by a transport multiplexer and repacketizer and broadcast to receiver stations, via satellite. The receiver stations receive the PES information and obtain the PTS. A receiver station multiplies the PTS by 300 and compares its local clock reference to that time. When the local clock reference and the PTS are identical, the PES audio and video information is displayed to the user according to the local clock reference.
摘要翻译：公开了一种通过卫星分配高分辨率电视（HDTV）和标清电视（SDTV）信号的系统和方法。在发送站处，MPEG-2视频编码器压缩视频信号，数字编码器对音频信号进行编码。压缩视频和编码音频耦合到PES打包器，PES分组器产生具有PES头部和PES有效载荷的视频和音频分组的基本数据流。在每个PES头部内是呈现时间戳（PTS），其表示有效载荷将显示给用户的时间。分组化的基本数据流由传输多路复用器和解码器复用在一起，并通过卫星广播到接收机站。接收站接收PES信息并获得PTS。接收站将PTS乘以300，并将其本地时钟参考值与该时间进行比较。当本地时钟参考和PTS相同时，PES音频和视频信息根据本地时钟参考显示给用户。

5. 发明授权

US06249319B1 Method and apparatus for finding a correct synchronization point within a data stream 失效
标题翻译：用于在数据流内找到正确的同步点的方法和装置
公开(公告)号：US06249319B1
公开(公告)日：2001-06-19
申请号：US09050274
申请日：1998-03-30
申请人： Lauren L. Post
发明人： Lauren L. Post
IPC分类号： H04N9475
CPC分类号： H04N21/4307 , H04N21/2368 , H04N21/4305 , H04N21/4341
摘要： A method in a data processing system for locating a correct synchronization point in a data stream containing a plurality of video data packets and a plurality of audio data packets. A data stream is monitored for an audio synchronization factor within an audio data packet and for a video synchronization factor within a video data packet. In response to detecting a video synchronization factor in the video data packet, a first audio data packet from the plurality of audio data packets after the video data packet is examined to determine whether the first audio data packet contains an audio synchronization factor. In response to detecting an audio synchronization factor in the audio data packet, a data packet immediately following the audio data packet is examined to determine whether the data packet is a video data packet containing a video synchronization factor. The synchronization point is located in the video data packet in response detecting an audio synchronization factor in the first audio data packet after the video data packet containing the video synchronization factor. The synchronization point is located in the audio data packet in response to detecting the video synchronization factor in a video data packet immediately after the audio data packet. The synchronization point is used to set a start point to begin presentation of the audio and video data from the data stream.
摘要翻译：一种数据处理系统中的方法，用于在包含多个视频数据分组和多个音频数据分组的数据流中定位正确的同步点。监视音频数据分组内的音频同步因子和视频数据分组内的视频同步因子的数据流。响应于检测到视频数据分组中的视频同步因子，检查在视频数据分组之后的多个音频数据分组中的第一音频数据分组，以确定第一音频数据分组是否包含音频同步因子。响应于检测到音频数据分组中的音频同步因子，检查紧跟在音频数据分组之后的数据分组，以确定数据分组是否是包含视频同步因子的视频数据分组。响应于在包含视频同步因子的视频数据分组之后检测第一音频数据分组中的音频同步因子，同步点位于视频数据分组中。响应于在紧接音频数据包之后的视频数据分组中检测到视频同步因子，同步点位于音频数据分组中。同步点用于设置开始点以开始从数据流中呈现音频和视频数据。

6. 发明授权

US06757024B2 Timing recovery apparatus and method for digital TV using envelope of timing error 有权
标题翻译：数字电视使用定时误差包络的定时恢复装置及方法
公开(公告)号：US06757024B2
公开(公告)日：2004-06-29
申请号：US09754356
申请日：2001-01-05
申请人： Tae Won Lee
发明人： Tae Won Lee
IPC分类号： H04N9475
CPC分类号： H04N21/4305 , H04N5/4401
摘要： A timing recovery apparatus and method for a digital TV is disclosed. The timing recovery apparatus includes: a symbol synchronization unit for determining the bandwidth of a timing recovery loop in a plurality of steps according to a convergence degree; and a timing lock detector for detecting a lock using a reference value calculated by the envelope of a timing error, whereby the envelope of the timing error calculated according to a channel state is used as a reference value for thereby preventing a lock error and assuring a rapid and accurate convergence characteristic.
摘要翻译：公开了一种用于数字电视的定时恢复装置和方法。定时恢复装置包括：符号同步单元，用于根据收敛度确定多个步骤中的定时恢复环路的带宽; 以及定时锁定检测器，用于使用由定时误差的包络计算的参考值来检测锁定，由此将根据通道状态计算的定时误差的包络用作参考值，从而防止锁定错误并确保快速准确的收敛特性。

7. 发明授权

US06741290B1 Processing coded video 失效
标题翻译：处理编码视频
公开(公告)号：US06741290B1
公开(公告)日：2004-05-25
申请号：US09485342
申请日：2000-04-04
申请人： Nicholas Dominic Wells
发明人： Nicholas Dominic Wells
IPC分类号： H04N9475
CPC分类号： G11B27/031 , G06T9/007 , G11B27/036 , G11B27/10 , H04N21/23406 , H04N21/23424 , H04N21/23608 , H04N21/242 , H04N21/2665
摘要： A method of processing coded video, for example by inserting generated frames, or adjusting values in timing fields, or adjusting the time at which it is output, to adjust the timing of output of decoded video from a decoder receiving the coded video is disclosed, together with corresponding apparatus. The outputting apparatus may be included in a multiple-source video system, to enable multiple video sources to be synchronized. The output video can be synchronized to a studio reference clock.
摘要翻译：公开了一种处理编码视频的方法，例如通过插入生成的帧或调整定时域中的值或调整其输出的时间来调整从接收编码视频的解码器输出解码视频的定时，以及相应的装置。输出装置可以包括在多源视频系统中，以使多个视频源能够同步。输出视频可以同步到工作室参考时钟。

8. 发明授权

US06538700B1 Synchronizing conversion apparatus and method as well as recording medium 失效
标题翻译：同步转换装置和方法以及记录介质
公开(公告)号：US06538700B1
公开(公告)日：2003-03-25
申请号：US09602828
申请日：2000-06-23
申请人： Masashi Ohta , Kyoko Fukuda , Hiroshi Kobayashi
发明人： Masashi Ohta , Kyoko Fukuda , Hiroshi Kobayashi
IPC分类号： H04N9475
CPC分类号： H04N5/0736 , H04N5/147
摘要： The invention provides a synchronizing conversion apparatus wherein outpacing compensation can be executed with a circuit construction including a comparatively small number of components. A read control circuit produces a read control signal including a read address and a read timing based on an outpacing detection signal from a phase comparison circuit, which is generated taking a time required for processing of a memory access arbitration circuit into consideration, and a scene change detection signal from a scene change detection circuit. The read control signal is outputted to the memory access arbitration circuit. The memory access arbitration circuit arbitrates requests from a write control circuit and the read control circuit to control writing into and reading out from a frame memory.
摘要翻译：本发明提供了一种同步转换装置，其中可以用包括相对较少数量的部件的电路结构执行超速补偿。读取控制电路产生包括读取地址和读取定时的读取控制信号，该读取定时基于来自相位比较电路的超前检测信号，该相位比较电路考虑了对存储器访问仲裁电路进行处理所需的时间所产生的场景，以及场景改变来自场景变化检测电路的检测信号。读取控制信号被输出到存储器访问仲裁电路。存储器访问仲裁电路仲裁来自写控制电路和读控制电路的请求，以控制写入和从帧存储器读出。

9. 发明授权

US06285405B1 System and method for synchronizing data signals 有权
标题翻译：用于同步数据信号的系统和方法
公开(公告)号：US06285405B1
公开(公告)日：2001-09-04
申请号：US09172430
申请日：1998-10-14
申请人： Donald D. Binford, Jr. , Matthew W. Korte , William J. Jackman
发明人： Donald D. Binford, Jr. , Matthew W. Korte , William J. Jackman
IPC分类号： H04N9475
CPC分类号： H04N21/2368 , H04N5/04 , H04N5/4401 , H04N7/152 , H04N21/242 , H04N21/4307 , H04N21/4341
摘要： A system for dynamically determining and introducing time delay values for synchronizing different data signals. For transmitting the data signals, encoding time delay is measured in one encoder, a target encoder time delay value is determined, and the target encoder time delay value is utilized in another encoder to delay transmission of one data signal relative to the transmission of the other data signal. When encoded data signals are received and processed for presentation, the time required to decode a first data signal in a first decoder is measured, a target decoder time delay value is determined based on the time required to decode the first data signal, and the target decoder time delay value is utilized to delay presentation of a second data signal relative to the presentation of the first data signal.
摘要翻译：一种用于动态地确定和引入用于同步不同数据信号的时间延迟值的系统。为了发送数据信号，在一个编码器中测量编码时间延迟，确定目标编码器时间延迟值，并且目标编码器时间延迟值用于另一个编码器以延迟一个数据信号相对于另一个的传输的传输数据信号。当接收和处理编码数据信号以进行呈现时，测量解码第一解码器中的第一数据信号所需的时间，基于解码第一数据信号所需的时间和目标，确定目标解码器时间延迟值解码器时间延迟值用于相对于第一数据信号的呈现来延迟第二数据信号的呈现。

10. 发明授权

US06229573B1 Synchronization control circuit 失效
标题翻译：同步控制电路
公开(公告)号：US06229573B1
公开(公告)日：2001-05-08
申请号：US09263489
申请日：1999-03-08
申请人： Koichi Sato , Takashi Suzuki , Riichiro Yoshida
发明人： Koichi Sato , Takashi Suzuki , Riichiro Yoshida
IPC分类号： H04N9475
CPC分类号： H04N5/12
摘要： In a synchronization control circuit according to the present invention, an image can smoothly be switched to another without distortion due to switching between sync signals to be displayed. The phases of sync signals of input video signals A and B are compared with each other in a phase difference detecting section, and the sync signal of one (B) of the signals is matched with that of the other signal A. When signal A is switched to signal B, an image is displayed in response to the corrected sync signal of signal B (corresponding to the sync signal matched with that of signal A). As a result, the synchronization state of signal A is maintained on a display screen, and the image can smoothly be switched without distortion.
摘要翻译：在根据本发明的同步控制电路中，由于要显示的同步信号之间的切换，图像可以平滑地切换到另一个而不失真。输入视频信号A和B的同步信号的相位在相位差检测部分中相互比较，一（B）个信号的同步信号与其他信号A的同步信号相匹配。当信号A为切换到信号B，响应于校正的信号B的同步信号（对应于与信号A的同步信号相匹配的同步信号）显示图像。结果，信号A的同步状态保持在显示屏幕上，并且可以平滑地切换图像而不失真。

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