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    • 2. 发明公开
    • Signal processing method and apparatus
    • 信号处理方法和装置
    • EP0072533A3
    • 1984-02-22
    • EP82107273
    • 1982-08-11
    • Battelle-Institut e.V.
    • Schmalfuss, Harald, Dr.Götz, Hans-Joachim
    • H04N05/14H04N09/535
    • H04N5/14
    • Zur Ver- und Bearbeitung von Signalen, insbesondere von Videosignalen, wird zum Zwecke einer zweidimensiona len Filterung das Eingangssignal einerseits mit der Impul santwort einer Zeile gefaltet und andererseits um die Dauer einer Zeile verzögert. Bei der Faltung wird das Signal für jeden Koeffizienten der Impulsantwort einer Zeile jeweils um die Dauer eines Bildpunktes verzogert, mit dem betreffenden Koeffizienten der Impulsantwort multipliziert und das Ergeb nis aufsummiert. Dieser Vorgang wird für jede Zeile der Impulsantwort wiederholt und alle Faltungsergebnisse wer den aufsummiert. Das Ergebnis der Summation entspricht dem Signal eines Bildes, das mit einem zweidimensionalen, beliebig reellen Punktbild gefaltet wurde.
      Gemäß einem alternativen Verfahren wird das Ein gangssignal auf N Leitungen eingespeist. Die Zahl N wird entsprechend der gewünschten Genauigkeit des kontinuierli chen Filterverlaufs festgelegt. In jeder Leitung wird das Signal mit einer vorgebbaren Trägerfrequenz moduliert gefiltert, demoduliert und anschließend verstärkt bzw. abge schwächt, und die resultierenden Signale werden aufsum miert schwächt. Zur zweidimensionalen Filterung wird die gesamte Signalbandbreite rotierend angetastet und anschließend an die Filterung die Rotation rückgängig gemacht.
    • 4. 发明公开
    • Delay circuit arrangements
    • 延迟电路安排
    • EP0102773A3
    • 1985-07-03
    • EP83304600
    • 1983-08-09
    • SONY CORPORATION
    • Tanaka, Sadaaki c/o Patent Division
    • H04N05/14
    • H04N5/208
    • A delay circuit arrangement comprises modulating means (41A, 41 B) for effecting contour modulation of a video signal using a signal from a carrier oscillator (50) as a carrier, delay means (43) for delaying the modulated output of the modulating means (41A, 41B), a variable phase shifter (52) for phase shifting the carrier oscillator output signal, demodulating means (45A, 45B) for effecting demodulation by synchronous detection using the output of the variable phase shifter (52) as a synchronizing signal, an adder (47) for superimposing a reference signal on a first demodulated signal from the demodulating means (45A, 45B) corresponding to a first input signal to the modulating means (41A, 41B) and supplying the resultant signal as a second input signal to the modulating means (41A, 41 B), and control means (54, 55, 56) for controlling the amount of phase shift by the variable phase shifter (52) according to the reference signal demodulated by the demodulating means (45A, 45B), wherein the demodulating means (45A, 45B) produces a first demodulated signal delayed relative to the first input signal supplied to the modulating means (41A, 41B) by an amount determined by the delay means (43) and a second demodulated signal delayed relative to the first input signal by double the amount.
    • 6. 发明公开
    • Charge transfer device incorporating Laplacian thresholding with a time delay and integration imaging array
    • 带时间延迟和集成成像阵列的LAPLACIAN阈值充电传输装置
    • EP0030292A3
    • 1983-03-30
    • EP80107145
    • 1980-11-18
    • International Business Machines Corporation
    • White, James Merrill
    • H04N05/30H01L27/14H04N05/14
    • H04N5/37206
    • A charge transfer device incorporating Laplacian thresholding with an imaging array (1) operated in delay and integration mode to generate an array of charge packets corresponding to the light intensity at the picture elements of an irradiating image. The charge packets are gated in parallel to a line image storage array (7) that stores n rows of charge packets in a columnar relation. A replicator circuit (11) generates a replicated sum charge for each column of charge packets of the line image storage array. Each replicated sum charge corresponds to the sum of the n charges stored in a column (13) at a particular instant in time and the charge stored at the (n+1)/2 position of each column is the middle charge for the associated replicated sum charge. Parallel delay gating electrodes (15) gate a row of replicated sum charges to an area average serial shift register (17) at the same time that a row of corresponding middle charges is gated into a focused element serial shift register (9). The serial shift registers are gated synchronously in a serial fashion and, as the registers (9, 17) are gated, the endmost n replicated sum charges are summed by a horizontal summer (26) and 1/n 2 of the sum is subtracted by a comparator (23) from an associated central charge stored in the focused element serial shift register (9). The difference is the Laplacian for the central charge. The output of the focused element serial shift register, the summer output, and the Laplacian uare useful for subsequent image processing.
    • 一种电荷转移装置,其包括具有以延迟和积分模式操作的成像阵列(1)的拉普拉斯阈值,以产生对应于照射图像的像素处的光强度的电荷分组阵列。 电荷包被并行地与存储有n行电荷包的列图像存储阵列(7)进行选通。 复制器电路(11)为行图像存储阵列的每列电荷包生成复制和电荷。 每个复制和电荷对应于在特定时刻存储在列(13)中的n个电荷的和,并且存储在每列的(n + 1)/ 2位置处的电荷是相关联的复合总和的中间电荷 收费。 并行延迟选通电极(15)将一行复制和电荷门控到区域平均串行移位寄存器(17),同时将一行相应的中间电荷门控到聚焦元件串行移位寄存器(9)中。 串行移位寄存器以串行方式同步门控,并且当寄存器(9,17)被选通时,最终的n个复制和电荷由水平夏令(26)相加,并且和的1 / n <2 由比较器(23)从存储在聚焦元件串行移位寄存器(9)中的相关联的中央电荷减去。 不同之处在于中央收费的拉普拉斯(Laplacian)。 聚焦元件串行移位寄存器,夏季输出和拉普拉斯算子的输出对后续图像处理有用。
    • 10. 发明公开
    • Motion-adaptive interpolation method for video signal and device for implementing the same
    • 用于视频信号的运动自适应插值方法和用于实现该信号的装置
    • EP0160547A3
    • 1988-05-18
    • EP85302986
    • 1985-04-26
    • NEC CORPORATION
    • Furukawa, Akihiro
    • H04N05/14H04N07/137
    • H04N19/577H04N5/145H04N19/587
    • A motion video signal (2000), especially a frame-skipped signal is interpolated by detecting motion vectors in a detector (15). A motion estimation circuit (16) computes a representative motion'vector which is used to control the interpolation within a storage and computation unit (100) in which several frames are stored in a buffer (11) and read out by a speed matching circuit (12) in accordance with a scanning speed signal (1012) from a control generator (10). A frame of the video signal is also stored in a frame memory (18) which is addressed by an address generator (17) under control of the representative motion vector from the estimation circuit (16) to introduce a corresponding shift and thereby effect motion adaptive interpolation. The control generator (10) also controls a change-over circuit (14) to select the signal from the frame memory (18) or as read out from the buffer (11). Various embodiments of the motion estimation circuit (16) are described. All implement the principle of modifying the representative vector in such a manner that its frame to frame variation is limited to a predetermined range. This avoids jerky interpolation.
    • 通过检测器(15)中的运动矢量来内插运动视频信号(2000),特别是帧跳过信号。 运动估计电路(16)计算用于控制存储和计算单元(100)内的插值的代表运动矢量,其中若干帧被存储在缓冲器(11)中并由速度匹配电路(12)读出 )根据来自控制发生器(10)的扫描速度信号(1012)。 视频信号的帧也被存储在由来自估计电路(16)的代表性运动矢量的控制下由地址发生器(17)寻址的帧存储器(18)中,以引入相应的移位,从而影响运动自适应 插值。 控制发生器(10)还控制切换电路(14)来选择来自帧存储器(18)的信号或从缓冲器(11)读出。 描述运动估计电路(16)的各种实施例。 所有这些都实现了修改代表向量的原理,使得其帧间变化被限制在预定范围内。 这样可以避免剧烈的内插。