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1. 发明公开

EP0102773A3 Delay circuit arrangements 失效
标题翻译：延迟电路安排
公开(公告)号：EP0102773A3
公开(公告)日：1985-07-03
申请号：EP83304600
申请日：1983-08-09
申请人： SONY CORPORATION
发明人： Tanaka, Sadaaki c/o Patent Division
IPC分类号： H04N05/14
CPC分类号： H04N5/208
摘要： A delay circuit arrangement comprises modulating means (41A, 41 B) for effecting contour modulation of a video signal using a signal from a carrier oscillator (50) as a carrier, delay means (43) for delaying the modulated output of the modulating means (41A, 41B), a variable phase shifter (52) for phase shifting the carrier oscillator output signal, demodulating means (45A, 45B) for effecting demodulation by synchronous detection using the output of the variable phase shifter (52) as a synchronizing signal, an adder (47) for superimposing a reference signal on a first demodulated signal from the demodulating means (45A, 45B) corresponding to a first input signal to the modulating means (41A, 41B) and supplying the resultant signal as a second input signal to the modulating means (41A, 41 B), and control means (54, 55, 56) for controlling the amount of phase shift by the variable phase shifter (52) according to the reference signal demodulated by the demodulating means (45A, 45B), wherein the demodulating means (45A, 45B) produces a first demodulated signal delayed relative to the first input signal supplied to the modulating means (41A, 41B) by an amount determined by the delay means (43) and a second demodulated signal delayed relative to the first input signal by double the amount.

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