会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality
    • 用于编写数据错误的系统和方法,以便于验证错误检测或纠正代码功能
    • US20040225932A1
    • 2004-11-11
    • US10435147
    • 2003-05-10
    • Sahir S. HodaBrad F. BassNathan D. ZelleAnand V. Kamannavar
    • H04L001/24
    • H04L1/241
    • In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.
    • 在一个实施例中,本发明涉及一种用于将错误插入数据以便于验证错误检测算法的方法。 该方法包括:接收多个比特的数据损坏命令; 从数据损坏命令确定用于数据损坏的多个位内的多个位字段; 确定所述多个位字段中的每一个的最小和最大错误数; 确定要插入的错误的总数; 在随机位置将最小数量的错误插入到多个位字段的每一个中; 并且随机地将附加的错误插入到受到最大错误数量的多个位字段中,直到插入错误的总数为止。
    • 5. 发明申请
    • Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same
    • 具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
    • US20040205447A1
    • 2004-10-14
    • US10815505
    • 2004-04-01
    • Min-sang ParkJin-seok KwakSeong-jin Jang
    • G01R031/28H04L001/08H04L001/22H04L001/24
    • H03K19/00346
    • Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
    • 集成电路装置包括其中的数据反转电路,其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。 数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入 数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半,输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为 分别大于二阶输入数据组的二分之一。