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1. 发明专利

CZ3255U1 Circuit vector analyzer 未知
公开(公告)号：CZ3255U1
公开(公告)日：1995-06-14
申请号：CZ320994
申请日：1994-11-25
申请人： HOFFMANN KAREL DOC ING CSC , SKVOR ZBYNEK ING CSC
发明人： HOFFMANN KAREL DOC ING CSC , SKVOR ZBYNEK ING CSC
IPC分类号： G01R27/28 , G01R29/00 , H04B3/46 , H04B3/493 , H04L1/24 , G01R027/28 , G01R029/00 , H04B003/46 , H04L001/24

2. 发明申请

US20020166097A1 Method and apparatus for increasing the effective range of a communication link in a wireless communication system 有权
标题翻译：一种用于增加无线通信系统中的通信链路的有效范围的方法和装置
公开(公告)号：US20020166097A1
公开(公告)日：2002-11-07
申请号：US09817731
申请日：2001-03-26
发明人： Lars Johan Persson , Athanasios A. Kasapi
IPC分类号： G06F011/00 , H04L001/08 , H04L001/22 , H04L001/24
CPC分类号： H04L1/20 , H04B7/0857 , H04B7/0871 , H04B7/0874 , H04B7/0894 , H04B7/12 , H04B17/309 , H04L1/06
摘要： A method is presented comprising identifying a weak component in a wireless communication link, instructing a transmitter of the weak component to invoke repetition coding, and selectively combining signals received via multiple antennae on multiple channels to recover information contained in the transmitted signal.
摘要翻译：提出了一种方法，其包括识别无线通信链路中的弱分量，指示弱分量的发射机调用重复编码，以及选择性地组合在多个信道上经由多个天线接收的信号，以恢复发送信号中包含的信息。

3. 发明申请

US20040213160A1 OAM echo messaging to verify a service-based network distribution path 有权
标题翻译： OAM回波消息传递，以验证基于服务的网络分发路径
公开(公告)号：US20040213160A1
公开(公告)日：2004-10-28
申请号：US10833823
申请日：2004-04-27
申请人： Alcatel IP Networks, Inc.
发明人： Joe Regan , Vach Kompella , Wenao Hu
IPC分类号： H04L001/24 , H04L012/28
CPC分类号： H04L43/00 , H04L43/0811 , H04L43/0817 , H04L43/0864 , H04L43/10 , H04L69/22
摘要： Echo messaging for operation, administration, and management of a service-based distribution path and associated services are disclosed. Service-based distribution paths or transport tunnels include services mapped or bound to a path associated with the transport tunnel. Echo messaging provides OAM capabilities to monitor the operational state of a service-based distribution path, including determining configuration, connectivity, and other characteristics of the path and associated services that transport data. OAM functions provided by echo messaging enable OAM functions despite service volume along a core network, path or set of paths.
摘要翻译：公开了用于基于服务的分发路径和相关服务的操作，管理和管理的回波消息。基于服务的分发路径或传输隧道包括映射或绑定到与传输隧道相关联的路径的服务。回声消息提供OAM功能来监视基于业务的分发路径的运行状态，包括确定路由和传输数据的相关服务的配置，连接性和其他特性。回波消息提供的OAM功能使OAM功能尽可能沿着核心网络，路径或路径集合进行服务卷。

4. 发明申请

US20040225932A1 Systems and methods for scripting data errors to facilitate verification of error detection or correction code functionality 失效
标题翻译：用于编写数据错误的系统和方法，以便于验证错误检测或纠正代码功能
公开(公告)号：US20040225932A1
公开(公告)日：2004-11-11
申请号：US10435147
申请日：2003-05-10
发明人： Sahir S. Hoda , Brad F. Bass , Nathan D. Zelle , Anand V. Kamannavar
IPC分类号： H04L001/24
CPC分类号： H04L1/241
摘要： In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.
摘要翻译：在一个实施例中，本发明涉及一种用于将错误插入数据以便于验证错误检测算法的方法。该方法包括：接收多个比特的数据损坏命令; 从数据损坏命令确定用于数据损坏的多个位内的多个位字段; 确定所述多个位字段中的每一个的最小和最大错误数; 确定要插入的错误的总数; 在随机位置将最小数量的错误插入到多个位字段的每一个中; 并且随机地将附加的错误插入到受到最大错误数量的多个位字段中，直到插入错误的总数为止。

5. 发明申请

US20040205447A1 Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same 有权
标题翻译：具有其中具有多位预取结构的数据反转电路的集成电路器件及其操作方法
公开(公告)号：US20040205447A1
公开(公告)日：2004-10-14
申请号：US10815505
申请日：2004-04-01
发明人： Min-sang Park , Jin-seok Kwak , Seong-jin Jang
IPC分类号： G01R031/28 , H04L001/08 , H04L001/22 , H04L001/24
CPC分类号： H03K19/00346
摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.
摘要翻译：集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为分别大于二阶输入数据组的二分之一。

6. 发明申请

US20040117692A1 High speed capture and averaging of serial data by asynchronous periodic sampling 有权
标题翻译：通过异步周期采样高速捕获和平均串行数据
公开(公告)号：US20040117692A1
公开(公告)日：2004-06-17
申请号：US10319116
申请日：2002-12-13
发明人： Charles M. Sweet
IPC分类号： G06F011/00 , H04L001/08 , H04L001/22 , H04L001/24
CPC分类号： G01R31/31709 , G01R31/31919 , G01R31/31926 , H04L1/24
摘要： An apparatus and process for measuring, testing, and/or characterizing high-speed bit streams includes repeating a serial bit steam and repetitively undersampling the repeated bit stream at a plurality of timing locations. Samples for each timing location are separately accumulated, and accumulated values are examined to determine the probability of the bit stream being high or low at each timing location. Identification of a periodic bit stream as well as measurement of jitter and other timing characteristics can then be measured.
摘要翻译：用于测量，测试和/或表征高速比特流的装置和过程包括在多个定时位置重复串行比特流并重复地对所述重复比特流进行低次采样。每个定时位置的样本被分别累积，并且检查累加值以确定每个定时位置处的比特流高或低的概率。然后可以测量周期位流的识别以及抖动和其它定时特性的测量。

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