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1. 发明授权

US06771670B1 Time-alignment apparatus and method for time-aligning data frames of a plurality of channels in a telecommunication system 有权
标题翻译：一种用于在电信系统中对多个信道的数据帧进行时间对准的时间对准装置和方法
公开(公告)号：US06771670B1
公开(公告)日：2004-08-03
申请号：US09671616
申请日：2000-09-28
申请人： Jürgen Pfahler , Peter Jentsch
发明人： Jürgen Pfahler , Peter Jentsch
IPC分类号： H04J306
CPC分类号： H04B7/2678 , H04W56/005
摘要： In a telecommunication system where data frames of a plurality of channels (CH1,CH2. . . CHn) arrive with respective different time-offsets with respect to a common synchronization clock (WR, R/W, RD, T) of an internal frame structure of a decoder (DEC), three frame memories (RAM1, RAM2, RAM3) are used for performing a time-alignment of the data frames. The data frames are respectively written to two frame memories (RAM1, RAM2) having a read state and a reading of one frame memory (RAM3) is performed beginning with the occurrence of the common synchronization clock (T). A cyclic switching of the read/write state of the frame memories (RAM1, RAM2, RAM3) is performed, such that always two frame memories (RAM1, RAM2) are in a write-state (WR) and one frame memory (RAM3) is in a read-state (RD) The frame memory (RAM3) in the read-state is read out synchronized to the common synchronization clock.
摘要翻译：在多个信道（CH1，CH2 ... CHn）的数据帧相对于内部帧的公共同步时钟（WR，R / W，RD，T））到达不同时间偏移的电信系统中，使用解码器（DEC）的结构，三帧存储器（RAM1，RAM2，RAM3）用于执行数据帧的时间对准。数据帧分别被写入具有读取状态的两个帧存储器（RAM1，RAM2），并且从公共同步时钟（T）的出现开始执行一个帧存储器（RAM3）的读取。执行帧存储器（RAM1，RAM2，RAM3）的读/写状态的循环切换，使得总是两个帧存储器（RAM1，RAM2）处于写状态（WR）和一帧存储器（RAM3）处于读取状态（RD）读取状态的帧存储器（RAM3）被读出与公共同步时钟同步。

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