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1. 发明专利

CZ3518U1 Circuit arrangement of electronic time switch of single-phase alternating current 未知
公开(公告)号：CZ3518U1
公开(公告)日：1995-08-16
申请号：CZ376295
申请日：1995-03-30
申请人： MATECHA MIROSLAV
发明人： MATECHA MIROSLAV
IPC分类号： H03K17/00 , H03K17/28 , H03K017/00 , H03K017/28

2. 发明专利

CZ8126U1 Logic supporting circuit of semiconductor switching element without own feeding 未知
公开(公告)号：CZ8126U1
公开(公告)日：1999-02-17
申请号：CZ803498
申请日：1998-05-13
申请人： HOSINSKY MILOS
发明人： HOSINSKY MILOS
IPC分类号： H03K17/00 , H03K17/51 , H03K17/56 , H03K017/00 , H03K017/51 , H03K017/56

3. 发明专利

CZ8006U1 Circuit arrangement for combined switching on/switching off and timing using a single contact 未知
公开(公告)号：CZ8006U1
公开(公告)日：1998-11-10
申请号：CZ803598
申请日：1998-05-13
申请人： HOSINSKY MILOS
发明人： HOSINSKY MILOS
IPC分类号： H03K17/00 , H03K17/28 , H03K017/00 , H03K017/28

4. 发明专利

CZ5326U1 Circuit arrangement for switching automatic control of vacuum cleaner suction power with switch-on signaling thereof 未知
公开(公告)号：CZ5326U1
公开(公告)日：1996-10-22
申请号：CZ565996
申请日：1996-08-20
申请人： ETA A S HLINSKO
发明人： AKRMAN VNISLAV
IPC分类号： H03K17/00 , G05F1/66 , H03K017/00 , G05F001/66

5. 发明申请

US20040061637A1 Sample-and-hold amplifier circuit and pipelined A/D and D/A converters using sample hold amplification circuit 失效
标题翻译：采样保持放大器电路和流水线A / D和D / A转换器使用采样保持放大电路
公开(公告)号：US20040061637A1
公开(公告)日：2004-04-01
申请号：US10609626
申请日：2003-07-01
申请人： Sharp Kabushiki Kaisha
发明人： Yoshihisa Fujimoto
IPC分类号： H03M001/38 , H03K005/00 , H03K017/00
CPC分类号： H03M1/442 , G11C27/026 , H03F3/45977 , H03K5/2481 , H03K5/249
摘要： A sample-and-hold amplifier circuit of the present invention has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (null1), the first and second switches are switched to the null1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. This allows to carry out the sampling so that the first and second capacitors are charged by predetermined electrical charges. During the second operation phase (null2), the first and second switches are switched to the null2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive. This allows that the voltage thus sampled is subjected to the operational amplification. During the next first operation phase, the switch for connecting or cutting off the connection is nonconductive, thereby holding the voltage (VOUT), that has been subjected to the operational amplification, at the output terminal of the operational amplifier stage. This allows to provide a sample-and-hold amplifier circuit that can realize the low power consumption.
摘要翻译：本发明的采样保持放大器电路具有一个开关，设置在运算放大器级和反相放大级之间，用于连接或切断运算放大器级和反相放大级的连接。在第一操作阶段（phi1）期间，第一和第二开关切换到phi1侧，第三开关导通，用于连接或切断连接的开关不导通。这允许执行采样，使得第一和第二电容器被预定的电荷充电。在第二操作阶段（phi2）期间，第一和第二开关切换到phi2侧，第三开关不导通，用于连接或切断连接的开关是导电的。这使得这样采样的电压经受操作放大。在下一个第一操作阶段，用于连接或切断连接的开关是不导通的，从而保持已经经受操作放大的电压（VOUT）在运算放大器级的输出端。这允许提供可实现低功耗的采样保持放大器电路。

6. 发明申请

US20030030481A1 Power module 失效
标题翻译：电源模块
公开(公告)号：US20030030481A1
公开(公告)日：2003-02-13
申请号：US10189561
申请日：2002-07-08
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takeshi Oumaru
IPC分类号： H03K017/00
CPC分类号： H05K7/1432 , H01L25/072 , H01L2224/48091 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A power module having a plurality of power devices arranged in parallel with each other and switched by gate signals with substantially equal electric potential. The power module includes: a collector electrode pattern, first and second power devices provided on the collector electrode pattern and each having a collector electrode connected to the collector electrode pattern; an emitter electrode pattern provided along the collector electrode pattern and having an emitter lead, and first and second connection means for connecting emitter electrodes on the first and second power devices and the emitter electrode pattern, respectively. The power module is characterized in that an inductance component of at least one of the first and second connection means is adjusted so that the inductance component between the emitter electrode on the first power device and the emitter lead is substantially equal to that between the emitter electrode on the second power device and the emitter lead.
摘要翻译：一种功率模块，具有彼此并联布置的多个功率器件，并且具有基本相等的电位的栅极信号切换。功率模块包括：集电极图案，设置在集电极图案上的每个具有与集电极图案连接的集电极的第一和第二功率元件; 沿着集电极图案设置并具有发射极引线的发射极电极图案，以及用于分别连接第一和第二功率器件上的发射极和发射极电极图案的第一和第二连接装置。功率模块的特征在于，调节第一和第二连接装置中的至少一个的电感分量，使得第一功率器件上的发射极和发射极之间的电感分量基本上等于发射极之间的电感分量在第二功率器件和发射极引线上。

7. 发明申请

US20030011410A1 Chopper type comparator 失效
标题翻译：斩波式比较器
公开(公告)号：US20030011410A1
公开(公告)日：2003-01-16
申请号：US10179892
申请日：2002-06-26
发明人： Masanori Koizumi
IPC分类号： H03K017/00
CPC分类号： H03K5/151 , G11C27/026 , H03K5/249
摘要： A chopper type comparator is equipped with an input switching circuit 1 that switches between an input voltage VIN and a reference voltage VRE, a capacitor C1, and an amplification circuit 11 that is formed from amplifiers (CMOS inverters) 12. The input switching circuit 1 is provided with a switch CT1 that turns on and off the input voltage VIN, and a switch CT2 that turns on and off the reference voltage VRE. Rising and falling of control signals to the P channel and N channel transistors of the switches CT1 and CT2 are simultaneously conducted, and an intersection of the rising and falling sections thereof coincide with a center of the amplitude of the drive signals.
摘要翻译：斩波型比较器配备有输入开关电路1，其在输入电压VIN和参考电压VRE之间切换，电容器C1和由放大器（CMOS反相器）12形成的放大电路11）。输入开关电路1 设置有导通和断开输入电压VIN的开关CT1和导通和截止参考电压VRE的开关CT2。控制信号向开关CT1和CT2的P沟道和N沟道晶体管的上升和下降同时导通，其上升和下降部分的交点与驱动信号的幅度的中心一致。

8. 发明申请

US20020011891A1 Switching control circuit 审中-公开
标题翻译：开关控制电路
公开(公告)号：US20020011891A1
公开(公告)日：2002-01-31
申请号：US09906350
申请日：2001-07-16
发明人： Han Martijn Schuurmans , Quino Alexander Sandifort
IPC分类号： H03K017/00
CPC分类号： H03K17/16 , H03K17/163 , H03K17/693
摘要： To switch a switch of an audio source for example the problem exists that switching noise can occur. The invention proposes a switching control circuit overcoming the problems of the prior art devices. The switching control circuit according to the invention comprises means to generate a switch control signal which comprises several transitions from high to low and vice versa during one operation from a first to a second state or vice versa.
摘要翻译：例如，为了切换音频源的开关，存在可能发生开关噪声的问题。本发明提出了克服现有技术装置的问题的开关控制电路。根据本发明的开关控制电路包括用于产生开关控制信号的装置，该开关控制信号在从第一状态到第二状态的一个操作期间包括从高到低的几个转换，反之亦然。

9. 发明申请

US20040008071A1 Rentention register for system-transparent state retention 有权
标题翻译：租用注册系统透明状态保留
公开(公告)号：US20040008071A1
公开(公告)日：2004-01-15
申请号：US10616207
申请日：2003-07-03
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T Mair
IPC分类号： H03K017/00
CPC分类号： H03K3/356008
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1nullM3; M1nullM4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a nulldon't carenull signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M1-M3; M1-M4）用于从正常功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于用于实现状态保持功能的高Vt晶体管（M1，M2，M5和M6; M3，M4，M5和M6）的操作状态而工作。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

10. 发明申请

US20030189455A1 CMOS transmission gate with high impedance at power off 失效
标题翻译： CMOS传输门在断电时具有高阻抗
公开(公告)号：US20030189455A1
公开(公告)日：2003-10-09
申请号：US10119101
申请日：2002-04-08
申请人： Exar Corporation
发明人： Bahram Fotouhi
IPC分类号： H03K017/00
CPC分类号： H03K17/302 , H03K17/6872 , H03K2217/0018
摘要： A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.
摘要翻译：一种在断电条件下具有高阻抗的传输门电路，其包括耦合在第一端子和第二端子之间的第一晶体管和耦合在第一端子和第二端子之间的第二晶体管。还包括一种控制电路，其被配置为监测第一端子上和第一电压源上的电压，该控制电路被配置为将第一和第二晶体管的栅极耦合到在断电期间将使第一和第二晶体管保持关闭的电压条件。

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