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1. 发明申请

US20040095164A1 POWER CONVERTER CIRCUITRY AND METHOD 有权
公开(公告)号：US20040095164A1
公开(公告)日：2004-05-20
申请号：US10295449
申请日：2002-11-14
发明人： Kent Kernahan , Elias Lozano , Daniel W. Yoder
IPC分类号： H03K005/00
CPC分类号： G11C27/02 , H03K5/133 , H03L7/0996
摘要： A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

2. 发明申请

US20040027174A1 Fast sample-and-hold peak detector circuit 有权
公开(公告)号：US20040027174A1
公开(公告)日：2004-02-12
申请号：US10601865
申请日：2003-06-24
申请人： ALCATEL
发明人： Ralph Ballentin , Frank Ilchmann
IPC分类号： H03K005/00
CPC分类号： G11C27/024 , G11C27/026
摘要： This invention relates to circuitry for detecting peak levels of signals and particularly fast hold and sample peak detectors for analyzing signals of generally arbitrary wave shape and form having a high precision, high slew-rate, very short retention, and a low distortion. The circuitry comprising a comparator circuit comprising two signal inputs and a signal output, where the output signal depends from the difference between the input signals, a sample and hold circuit comprising switching means controlled by said signal output for sampling and holding means for holding the output signal, a compensation circuit for compensating residual currents comprising emulating means for emulating residual currents caused by said comparator circuit influencing the functionality of said sample and hold circuit, and an unload circuit comprising a clearing means for decreasing the output signal of said sample and hold circuit.

3. 发明申请

US20030102892A1 Self calibrating register for source synchronoous clocking systems 失效
标题翻译：源同步计时系统的自校准寄存器
公开(公告)号：US20030102892A1
公开(公告)日：2003-06-05
申请号：US10007603
申请日：2001-12-05
发明人： Peter J. Meier , Gerald L. Esch JR.
IPC分类号： H03K005/00
CPC分类号： H03L7/0812 , H04L7/0337
摘要： A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.
摘要翻译：自校准寄存器。在代表性实施例中，公开了通过抵消系统不匹配的固有系统源来增加源同步输入/输出（I / O）数据速率的寄存器。位线路径和器件之间的系统不匹配的系统来源，例如印刷电路板路径长度，封装迹线长度，片上时钟路由，时钟偏移，器件导通电压等相对于参考时钟信号由数据信号的编程延迟。适当的延迟通过相移检测电路获得，然后由控制电路施加到信号延迟电路。

4. 发明申请

US20030076135A1 Track and hold circuit 失效
公开(公告)号：US20030076135A1
公开(公告)日：2003-04-24
申请号：US10280662
申请日：2002-10-25
申请人： AGILENT TECHNOLOGIES, INC.
发明人： Hisao Kakitani
IPC分类号： H03K005/00
CPC分类号： G11C27/026 , G11C27/024
摘要： In order to reduce harmonic distortion, a track and hold circuit comprising a MOS transistor switch, a hold capacitor, and a voltage stabilizer for biasing bulk potential of the MOS transistor switch at a certain voltage is disclosed.

5. 发明申请

US20020047728A1 Integrated circuit 审中-公开
标题翻译：集成电路
公开(公告)号：US20020047728A1
公开(公告)日：2002-04-25
申请号：US09839767
申请日：2001-04-20
发明人： Joachim Held , Thomas Steinecke
IPC分类号： G01R001/00 , H03K005/00 , H03D003/00
CPC分类号： H01L22/00 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is described which is distinguished by the fact that there is integrated in it an RF filter device which can prevent or restrict the propagation of high-frequency interference signals through lines carrying DC voltages or low-frequency voltages. As a result, interference with the operation of the integrated circuit and/or of other integrated circuits or of other components of the system containing the integrated circuit can be prevented in a very simple yet extremely effective manner.
摘要翻译：描述了集成电路，其特征在于集成有RF滤波器装置，该RF滤波器装置可以通过承载DC电压或低频电压的线路来防止或限制高频干扰信号的传播。结果，可以以非常简单但非常有效的方式来防止对集成电路和/或其他集成电路或包含集成电路的系统的其它部件的操作的干扰。

6. 发明申请

US20020024363A1 Sample-and-hold amplifier circuit and pipelined A/D and D/A converters using sample hold amplification circuit 失效
标题翻译：采样保持放大器电路和流水线A / D和D / A转换器使用采样保持放大电路
公开(公告)号：US20020024363A1
公开(公告)日：2002-02-28
申请号：US09932025
申请日：2001-08-20
发明人： Yoshihisa Fujimoto
IPC分类号： H03K005/00
CPC分类号： H03M1/442 , G11C27/026 , H03F3/45977 , H03K5/2481 , H03K5/249
摘要： A sample-and-hold amplifier circuit of the present invention has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (null1), the first and second switches are switched to the null1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. This allows to carry out the sampling so that the first and second capacitors are charged by predetermined electrical charges. During the second operation phase (null2), the first and second switches are switched to the null2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive. This allows that the voltage thus sampled is subjected to the operational amplification. During the next first operation phase, the switch for connecting or cutting off the connection is nonconductive, thereby holding the voltage (VOUT), that has been subjected to the operational amplification, at the output terminal of the operational amplifier stage. This allows to provide a sample-and-hold amplifier circuit that can realize the low power
摘要翻译：本发明的采样保持放大器电路具有一个开关，设置在运算放大器级和反相放大级之间，用于连接或切断运算放大器级和反相放大级的连接。在第一操作阶段（phi1）期间，第一和第二开关切换到phi1侧，第三开关导通，用于连接或切断连接的开关不导通。这允许执行采样，使得第一和第二电容器被预定的电荷充电。在第二操作阶段（phi2）期间，第一和第二开关切换到phi2侧，第三开关不导通，用于连接或切断连接的开关是导电的。这使得这样采样的电压经受操作放大。在下一个第一操作阶段，用于连接或切断连接的开关是不导通的，从而保持已经经受操作放大的电压（VOUT）在运算放大器级的输出端。这允许提供可以实现低功率的采样保持放大器电路

7. 发明申请

US20010026174A1 Self-timed switching for a digital power amplifier 有权
标题翻译：数字功率放大器的自定时切换
公开(公告)号：US20010026174A1
公开(公告)日：2001-10-04
申请号：US09796731
申请日：2001-02-28
申请人： Tripath Technology, Inc.
发明人： Cary L. Delano
IPC分类号： H03K005/00
CPC分类号： H03F3/2171 , H03F3/2173
摘要： An electronic device includes sampling circuitry and at least one switching device. Each switching device has resonance circuitry associated with the output terminal thereof. The resonance circuitry and the at least one switching device have at least one resonance oscillation associated therewith. The electronic device further comprises clock generation circuitry which generates a clock signal for the sampling circuitry at least in part from the at least one resonance oscillation.
摘要翻译：电子设备包括采样电路和至少一个开关装置。每个开关装置具有与其输出端子相关联的谐振电路。谐振电路和至少一个开关器件具有与其相关联的至少一个谐振振荡。电子设备还包括时钟产生电路，其至少部分地从至少一个谐振振荡产生用于采样电路的时钟信号。

8. 发明申请

US20040239378A1 Sample-and-hold with no-delay reset 有权
标题翻译：采样保持，无延迟复位
公开(公告)号：US20040239378A1
公开(公告)日：2004-12-02
申请号：US10889377
申请日：2004-07-12
发明人： Peter Bogner
IPC分类号： H03K005/00
CPC分类号： G11C27/026
摘要： An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase. During a sample phase a first storage device is charged to a voltage value proportional to an analog input signal, which voltage value is provided for a further circuit part of the integrated circuit in the hold phase. A second storage device is charged during a first cycle to a voltage value which is inverted relative to a final voltage value of the first storage device in the hold phase. In the sample phase of the next cycle following the first cycle, the second storage device is connected to the first storage device in order to discharge the first storage device.
摘要翻译：提供了一种具有采样保持装置的集成电路，其可以在连续的周期中操作，每个周期包括采样相位和保持相位。在采样阶段期间，第一存储设备被充电到与模拟输入信号成比例的电压值，该电压值被提供给处于保持阶段的集成电路的另外电路部分。第二存储装置在第一周期期间被充电到在保持阶段中相对于第一存储装置的最终电压值反相的电压值。在第一周期之后的下一周期的采样阶段中，第二存储装置连接到第一存储装置以便排出第一存储装置。

9. 发明申请

US20040155702A1 Active filter circuit arrangement 审中-公开
标题翻译：有源滤波器电路布置
公开(公告)号：US20040155702A1
公开(公告)日：2004-08-12
申请号：US10364478
申请日：2003-02-11
申请人： Siemens Elema AB
发明人： Peter Danielsson
IPC分类号： H03B001/00 , H04B001/10 , H03K005/00
CPC分类号： H03H11/1217 , A61B5/0428 , A61B5/7217
摘要： An active filter circuit for removing high frequency noise from an input signal, particularly RF noise from an ECG signal, has an active first circuit having an input and an output, an RC-filter network arranged in electrical connection with the input and a second circuit connected in a positive feedback loop with the RC-filter network and adapted to reduce high frequency signals at an output of the first active circuit.
摘要翻译：一种用于从输入信号去除高频噪声的有源滤波器电路，特别是来自ECG信号的RF噪声，具有有源输入和输出的有源第一电路，与输入端电连接的RC滤波器网络和第二电路连接在与RC滤波器网络的正反馈环路中，并适于减少第一有源电路的输出处的高频信号。

10. 发明申请

US20040119508A1 High speed track and hold amplifier for direct digital down-conversion 失效
标题翻译：高速跟踪和保持放大器，用于直接数字下转换
公开(公告)号：US20040119508A1
公开(公告)日：2004-06-24
申请号：US10323060
申请日：2002-12-18
发明人： James J. Komiak
IPC分类号： H03K005/00
CPC分类号： G11C27/026
摘要： An X-band capable track and hold amplifier capable of handling input frequencies of greater than 1 GHz, and as high as 15 GHz. The amplifier is built using a pseudomorphic high electron mobility transistor (PHEMT) process which gives high yield and uniformity.
摘要翻译：能够处理大于1GHz，高达15GHz的输入频率的具有X波段能力的轨道和保持放大器。放大器使用伪像高电子迁移率晶体管（PHEMT）工艺构建，其产生高产率和均匀性。

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