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1. 发明授权

US07586343B2 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US07586343B2
公开(公告)日：2009-09-08
申请号：US11800438
申请日：2007-05-04
申请人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
发明人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

2. 发明授权

US07724047B2 Semiconductor integrated circuit driving external FET and power supply incorporating the same 有权
标题翻译：驱动外部FET的半导体集成电路和并入其的电源
公开(公告)号：US07724047B2
公开(公告)日：2010-05-25
申请号：US11951692
申请日：2007-12-06
申请人： Eiji Nakagawa , Koji Miyamoto , Akira Aoki
发明人： Eiji Nakagawa , Koji Miyamoto , Akira Aoki
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K5/151
摘要： A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.
摘要翻译：一种半导体集成电路包括：开关控制电路，其具有第一晶体管和耦合到FET的第二晶体管，并且通过接通和关断所述第一晶体管和所述第二晶体管中的每一个来导通和关断所述FET，所述FET达到OFF 当第一晶体管处于导通状态并且第二晶体管处于截止状态时，当所述第一晶体管和所述第二晶体管处于截止状态时，所述偏置电路为所述FET提供用于关断所述FET的偏置电压; 并且保护控制电路通过接通第一晶体管并且当检测到异常时关闭第二晶体管而关断FET，并且在经过预定时间之后关闭第一晶体管和第二晶体管。

3. 发明授权

US07183816B2 Circuit and method for switching an electrical load on after a delay 有权
标题翻译：延迟后切换电气负载的电路和方法
公开(公告)号：US07183816B2
公开(公告)日：2007-02-27
申请号：US10997206
申请日：2004-11-24
申请人： Yannick Martelloni
发明人： Yannick Martelloni
IPC分类号： H03B1/10
CPC分类号： H03K17/167 , H03K19/0016
摘要： A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a first path, and a second electronic switching means (T2) in a second path, which is in parallel with it. The circuit also has a means (INV, OR, T5) for producing the electrical control variable (Ugate2) for the second switching means (T2), which determines the control variable (Ugate2) as a function of an electrical variable (U0,d) which occurs on the output side of the first switching means (T1) when switching on a load which can be connected downstream.
摘要翻译：用于接通可以连接到电路下游的电负载的电路（S1）包括第一路径中的第一电子切换装置（T 1）和第二路径中的第二电子切换装置（T 2）这与它并行。该电路还具有用于产生用于第二开关装置（T 2）的电气控制变量（U 2）的装置（INV，OR，T 5），其确定控制变量（U _{gate2 ）作为在第一开关装置（T1）的输出侧发生的电气变量（U0，D}

4. 发明授权

US08456229B2 Filter device 有权
标题翻译：过滤装置
公开(公告)号：US08456229B2
公开(公告)日：2013-06-04
申请号：US13414150
申请日：2012-03-07
申请人： Yusuke Takahashi
发明人： Yusuke Takahashi
IPC分类号： H03B1/10 , H03K5/00 , H04B1/10
CPC分类号： A61B5/721 , A61B5/024
摘要： A filter device includes a filter that separates a steady component and a non-steady component included in an input signal, a synthesis unit that synthesizes the separated steady component and the separated non-steady component according to a given ratio, and an evaluation unit that evaluates the magnitude of the amount of the non-steady component in the input signal, wherein the synthesis unit sets the given ratio to a first ratio in an instance in which the evaluation unit determines the amount of the non-steady component to be equal to or less than a predetermined reference, and sets the given ratio to a second ratio, in which the proportion of the non-steady component is less than that of the first ratio, in an instance in which the evaluation unit determines the amount of the non-steady component to be greater than the predetermined reference.
摘要翻译：滤波器装置包括：滤波器，其分离输入信号中包含的稳定分量和非稳定分量;合成单元，其根据给定的比率合成分离的稳定分量和分离的非稳定分量;以及评估单元，评估输入信号中的非稳定分量的大小，其中在评估单元将非稳定分量的量确定为等于的情况下，合成单元将给定比率设置为第一比率或小于预定参考值，并且将所述给定比率设置为所述非稳定分量的比例小于所述第一比率的比率，其中所述评估单元确定所述非稳定分量的量， - 稳定分量大于预定参考值。

5. 发明授权

US07474884B2 Receiver 有权
标题翻译：接收器
公开(公告)号：US07474884B2
公开(公告)日：2009-01-06
申请号：US11519426
申请日：2006-09-11
申请人： Martin Kristensson , Bjorn Ottersten , David Astély
发明人： Martin Kristensson , Bjorn Ottersten , David Astély
IPC分类号： H04B1/10 , H04B7/185 , H04L27/08 , H03D1/04 , H03D1/106 , H03K5/01 , H03K6/04 , H03B1/10 , H03L1/00 , H03L25/08 , H04J1/12 , H04J3/10 , H04J15/00
CPC分类号： H04B1/7073 , H04B1/1036 , H04B1/7101
摘要： The present invention relates to a method for a digital receiver and a receiver exploiting second order statistics for adaptive co-channel interference rejection in wireless communication. It uses digitally I, in phase, and Q, quadrature, branches of a received transmitted signal as input to the receiver, a coarse synchronization and a coarse frequency offset compensation have being performed on the signal. It comprises a means for derotation, means for separation, means for filtering, means for estimating and means for detecting transmitted symbols in the received signal. The invention thereby improving co-channel rejection in wireless communication, thus making it possible to increase the number of communication channels for frequencies used.
摘要翻译：本发明涉及一种用于数字接收机的方法和一种利用无线通信中的自适应同频干扰抑制的二阶统计的接收机。它使用接收发射信号的数字I，同相和Q正交分支作为对接收机的输入，对该信号执行了粗同步和粗频率偏移补偿。它包括用于解旋的装置，用于分离的装置，用于滤波的装置，用于估计的装置和用于检测接收信号中的发射符号的装置。因此，本发明改善了无线通信中的同频道抑制，从而可以增加所使用频率的通信信道的数量。

6. 发明授权

US07233616B1 Arrangement for initializing digital equalizer settings based on comparing digital equalizer outputs to prescribed equalizer outputs 有权
标题翻译：基于将数字均衡器输出与规定的均衡器输出进行比较来初始化数字均衡器设置的布置
公开(公告)号：US07233616B1
公开(公告)日：2007-06-19
申请号：US10002185
申请日：2001-12-05
申请人： Colin D. Nayler
发明人： Colin D. Nayler
IPC分类号： H03B1/10
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617 , H04L2025/03656 , H04L2025/03681
摘要： A physical layer transceiver, configured for retrieving signal samples from a prescribed network medium having an undetermined length, includes a digital feedforward equalizer, configured for generating equalized signal samples from the retrieved signal samples and based on supplied equalizer settings, and an equalizer controller. The equalizer controller is configured for supplying selected equalizer settings that overcome intersymbol interference encountered by transmission of the signal samples across the prescribed network medium. The equalizer controller is configured for supplying prescribed initial equalizer settings to the digital feedforward equalizer, receiving equalized signal samples from the digital feedforward equalizer, and selectively changing the prescribed initial equalizer settings based on comparing the equalized signal samples to a prescribed equalization threshold. The equalizer controller is configured for selectively repeating the changing of the equalizer settings until the equalized signal samples reach the prescribed equalization threshold.
摘要翻译：物理层收发器，被配置用于从具有未确定长度的规定网络介质中检索信号样本，包括数字前馈均衡器，被配置为从所检索的信号样本中产生均衡的信号样本，并且基于所提供的均衡器设置，以及均衡器控制器。均衡器控制器被配置为提供选择的均衡器设置，其克服通过规定的网络介质发送信号样本所遇到的符号间干扰。均衡器控制器被配置为向数字前馈均衡器提供规定的初始均衡器设置，从数字前馈均衡器接收均衡的信号样本，并且基于将均衡的信号样本与规定的均衡阈值进行比较来选择性地改变规定的初始均衡器设置。均衡器控制器被配置为选择性地重复均衡器设置的改变，直到均衡的信号样本达到规定的均衡阈值。

7. 发明授权

US07262641B2 Current differential buffer 有权
标题翻译：电流差动缓冲器
公开(公告)号：US07262641B2
公开(公告)日：2007-08-28
申请号：US11006364
申请日：2004-12-07
申请人： Gregory King
发明人： Gregory King
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K19/00384 , H03K19/0008 , H03K19/0016 , H03K19/00361 , H03K19/018521 , H04L25/0272
摘要： The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential pair configured to receive input signals and generate output signals. The first stage may also include adjustment circuitry coupled to the differential pair and configured to adjust an amount of current dissipated by the differential buffer. Further, a second stage may include current pulse circuitry coupled to the differential pair and the adjustment circuitry, wherein the current pulse circuitry is configured to generate a current pulse that is coincident with the switching of the differential pair. Finally, the second stage may also include grounding circuitry coupled to the current pulse circuitry and the differential pair, wherein the grounding circuitry is configured to receive the current pulse to prevent the output signals from switching during a transition of the output signals. As such, the differential buffer provides low or no static current dissipation with improved signal integrity for high-speed operation.
摘要翻译：本技术涉及用于操作差分缓冲器的方法和装置。在差分缓冲器中，第一级可以包括被配置为接收输入信号并产生输出信号的差分对。第一级还可以包括耦合到差分对并且被配置为调整由差分缓冲器消耗的电流量的调节电路。此外，第二级可以包括耦合到差分对和调整电路的电流脉冲电路，其中当前脉冲电路被配置为产生与差分对的切换一致的电流脉冲。最后，第二级还可以包括耦合到当前脉冲电路和差分对的接地电路，其中接地电路被配置为接收电流脉冲，以防止输出信号在输出信号的转变期间切换。因此，差分缓冲器提供低或无静态电流消耗，具有改进的信号完整性，用于高速操作。

8. 发明授权

US07224195B2 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US07224195B2
公开(公告)日：2007-05-29
申请号：US11009434
申请日：2004-12-09
申请人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
发明人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

9. 发明授权

US07113553B2 Low-complexity joint symbol CCK decoder 有权
标题翻译：低复杂度联合符号CCK解码器
公开(公告)号：US07113553B2
公开(公告)日：2006-09-26
申请号：US10382756
申请日：2003-03-05
申请人： Jeng-Hong Chen , Wei-Chung Peng
发明人： Jeng-Hong Chen , Wei-Chung Peng
IPC分类号： H03D3/22 , H03B1/10
CPC分类号： H04L23/02 , H04B1/7105 , H04B1/7113 , H04B1/7115 , H04B1/712 , H04B2001/70935
摘要： A method is provided for mitigating the multipath interference experienced by a present CCK symbol. This method first obtains a set of initial candidates for the present CCK symbol and a set of initial candidates for the next CCK symbol based on the ICI-corrected correlation outputs for the present and next CCK symbols, respectively. The method then obtains, for each of the candidates for the present CCK symbol, first ISI-mitigated correlation outputs where both the ICI due to the present CCK symbol and the ISI due to the next CCK symbol have been corrected. Thereafter, for each of the candidates for the present CCK symbol, and based on the first ISI-mitigated correlation outputs, the method obtains second ISI-mitigated correlation outputs where the ISI due to the previous CCK symbol has also been corrected. The present CCK symbol is then decoded based on the second ISI-mitigated correlation outputs.
摘要翻译：提供了一种用于减轻当前CCK符号经历的多路径干扰的方法。该方法首先分别基于当前和下一个CCK符号的ICI校正的相关输出，获得针对当前CCK符号的一组初始候选和下一个CCK符号的一组初始候选。然后，该方法针对当前CCK符号的每个候选者获得第一ISI减轻的相关输出，其中由于当前CCK符号引起的ICI和由于下一个CCK符号引起的ISI都被校正。此后，对于当前CCK符号的每个候选，并且基于第一ISI减轻的相关输出，该方法获得第二ISI减轻的相关输出，其中由于先前的CCK符号导致的ISI也被校正。然后基于第二ISI减轻的相关输出对当前的CCK符号进行解码。

10. 发明授权

US07107031B2 Co-channel interference rejection in a digital receiver 有权
标题翻译：数字接收机中的同频干扰抑制
公开(公告)号：US07107031B2
公开(公告)日：2006-09-12
申请号：US10296964
申请日：2001-05-30
申请人： Martin Kristensson , Bjorn Ottersten , Astel David
发明人： Martin Kristensson , Bjorn Ottersten , Astel David
IPC分类号： H04B1/10 , H04B7/185 , H04L27/08 , H03D1/04 , H03D1/106 , H03K5/01 , H03K6/04 , H03B1/10 , H03L1/00 , H03L25/08 , H04J1/12 , H04J3/10 , H04J15/00
CPC分类号： H04B1/7073 , H04B1/1036 , H04B1/7101
摘要： The present invention relates to a method for a digital receiver and a receiver exploiting second order statistics for adaptive co-channel interference rejection in wireless communication. It uses digitally I, in phase, and Q, quadrature, branches of a received transmitted signal as input to the receiver, a coarse synchronization and a coarse frequency offset compensation have being performed on the signal. It comprises a means for derotation, means for separation, means for filtering, means for estimating and means for detecting transmitted symbols in the received signal. The invention thereby improving co-channel rejection in wireless communication, thus making it possible to increase the number of communication channels for frequencies used.
摘要翻译：本发明涉及一种用于数字接收机的方法和一种利用无线通信中的自适应同频干扰抑制的二阶统计的接收机。它使用接收发射信号的数字I，同相和Q正交分支作为对接收机的输入，对该信号执行了粗同步和粗频率偏移补偿。它包括用于解旋的装置，用于分离的装置，用于滤波的装置，用于估计的装置和用于检测接收信号中的发射符号的装置。因此，本发明改善了无线通信中的同频道抑制，从而可以增加所使用频率的通信信道的数量。

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