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    • 1. 发明授权
    • Semiconductor integrated circuit driving external FET and power supply incorporating the same
    • 驱动外部FET的半导体集成电路和并入其的电源
    • US07724047B2
    • 2010-05-25
    • US11951692
    • 2007-12-06
    • Eiji NakagawaKoji MiyamotoAkira Aoki
    • Eiji NakagawaKoji MiyamotoAkira Aoki
    • H03B1/10H03K3/00
    • H03K5/151
    • A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.
    • 一种半导体集成电路包括:开关控制电路,其具有第一晶体管和耦合到FET的第二晶体管,并且通过接通和关断所述第一晶体管和所述第二晶体管中的每一个来导通和关断所述FET,所述FET达到OFF 当第一晶体管处于导通状态并且第二晶体管处于截止状态时, 当所述第一晶体管和所述第二晶体管处于截止状态时,所述偏置电路为所述FET提供用于关断所述FET的偏置电压; 并且保护控制电路通过接通第一晶体管并且当检测到异常时关闭第二晶体管而关断FET,并且在经过预定时间之后关闭第一晶体管和第二晶体管。
    • 2. 发明申请
    • Semiconductor Integrated Circuit Driving External FET and Power Supply Incorporating the Same
    • 半导体集成电路驱动外部FET和电源并入其中
    • US20080136466A1
    • 2008-06-12
    • US11951692
    • 2007-12-06
    • Eiji NakagawaKoji MiyamotoAkira Aoki
    • Eiji NakagawaKoji MiyamotoAkira Aoki
    • H03K3/00
    • H03K5/151
    • A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.
    • 一种半导体集成电路包括:开关控制电路,其具有第一晶体管和耦合到FET的第二晶体管,并且通过接通和关断所述第一晶体管和所述第二晶体管中的每一个来导通和关断所述FET,所述FET达到OFF 当第一晶体管处于导通状态并且第二晶体管处于截止状态时, 当所述第一晶体管和所述第二晶体管处于截止状态时,所述偏置电路为所述FET提供用于关断所述FET的偏置电压; 并且保护控制电路通过接通第一晶体管并且当检测到异常时关闭第二晶体管而关断FET,并且在经过预定时间之后关闭第一晶体管和第二晶体管。