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1. 发明授权

CN1004735B 半导体元件失效
公开(公告)号：CN1004735B
公开(公告)日：1989-07-05
申请号：CN87106746
申请日：1987-10-01
申请人： BBC勃朗·勃威力有限公司
发明人： C·克里斯蒂安·阿巴斯 , 延斯·戈布雷希特 , 霍斯特·格吕宁 , 扬·福博利尔
IPC分类号： H01L29/06 , H01L29/743
CPC分类号： H01L29/0834 , H01L24/32 , H01L29/0657 , H01L2224/32245 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/10158 , H01L2924/1301 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要：对一种在半导体衬底中具有各种不同掺杂层(2，3，4，5)的半导体元件进行了电气性能方面的改进，方法是用深腐蚀坑(10)局部减少载流区衬底的厚度，同时基本上保持半导体衬底原有的机械稳定性。

2. 发明授权

US4654691A Semiconductor device with field plate 失效
标题翻译：具有现场板的半导体器件
公开(公告)号：US4654691A
公开(公告)日：1987-03-31
申请号：US816979
申请日：1986-01-07
申请人： Toshikatsu Shirasawa , Yoshikazu Hosokawa
发明人： Toshikatsu Shirasawa , Yoshikazu Hosokawa
IPC分类号： H01L29/41 , H01L29/06 , H01L29/40 , H01L29/74 , H01L29/52 , H01L27/12 , H01L29/743
CPC分类号： H01L29/404 , H01L29/7436
摘要： Field plates for relaxing electric fields are provided for an active element in a semiconductor integrated circuit. A field plate integral with an electrode making ohmic contact with an elongated strip shaped diffusion region and extending beyond a pn-junction formed between the diffusion region and an adjacent region to surround the pn-junction has a larger width at its opposite ends than a width at its linear portions. A high breakdown voltage can be obtained by thus configuring the field plate without changing the diffusion region in size.
摘要翻译：为半导体集成电路中的有源元件提供用于放电电场的场板。与电极形成欧姆接触的电场板与细长带状扩散区域并延伸超过形成在扩散区域和相邻区域之间以围绕pn结的pn结的宽度在其相对端宽度大于宽度在其线性部分。通过这样构成场板可以在不改变扩散区域的情况下获得高的击穿电压。

3. 发明授权

US4595941A Protection circuit for integrated circuit devices 失效
标题翻译：集成电路器件保护电路
公开(公告)号：US4595941A
公开(公告)日：1986-06-17
申请号：US741703
申请日：1985-06-07
申请人： Leslie R. Avery
发明人： Leslie R. Avery
IPC分类号： H01L27/02 , H01L29/87 , H01L27/04 , H01L29/743 , H01L29/78 , H02H9/04
CPC分类号： H01L27/0251 , H01L29/87 , H01L29/749
摘要： The protection circuit is a four layer PNPN device which includes a PMOS IGFET. The device is designed to pass current to ground when large transients are imposed across its two external terminals, thereby protecting the integrated circuit.
摘要翻译：保护电路是包括PMOS IGFET的四层PNPN器件。该器件设计用于在其两个外部端子上施加大的瞬变时将电流传递到地，从而保护集成电路。

4. 发明授权

US5387806A GTO-thyristor 失效
标题翻译： GTO晶闸管
公开(公告)号：US5387806A
公开(公告)日：1995-02-07
申请号：US208814
申请日：1994-03-11
申请人： Guenther Franz
发明人： Guenther Franz
IPC分类号： H01L29/417 , H01L29/423 , H01L29/744 , H01L29/74 , H01L29/747 , H01L29/743
CPC分类号： H01L29/42308 , H01L29/41716 , H01L29/744
摘要： The semiconductor substrate of a GTO-Thyristor is structured at a cathode-side such that the cathode electrode lies in a first uppermost level of and in a second level lying there below. A gate contact lies in a third lowest level. Passivation layers extend only over the second and third levels. The cathode electrode also contacts the cathode emitter zone in the second level. It is overlapped there by the passivation layers.
摘要翻译： GTO晶闸管的半导体衬底被构造在阴极侧，使得阴极位于位于其下方的第一最高水平和第二水平。门接触位于第三低水平。钝化层仅在第二和第三层上延伸。阴极也接触第二级的阴极发射区。钝化层在那里重叠。

5. 发明授权

US4638553A Method of manufacture of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4638553A
公开(公告)日：1987-01-27
申请号：US784177
申请日：1985-10-04
申请人： Anders Nilarp
发明人： Anders Nilarp
IPC分类号： H01L21/285 , H01L21/60 , H01L21/78 , H01L21/302 , H01L29/743
CPC分类号： H01L21/76897 , H01L21/2855 , H01L21/78 , H01L2924/3011
摘要： The junctions of a plurality of semiconductor devices are formed in a common wafer. The upper surface of the common wafer is metallized for each of the individual devices by a nickel, chromium, nickel, silver metallizing system. Individual wafer elements are thereafter separated from the main wafer and their bottom surfaces are vacuum-alloyed to a molybdenum expansion plate. Thereafter, the outer periphery of the devices is tapered by grinding and the periphery is etched by hot potassium hydroxide without need to protect the upper metallizing from the etch. The caustic etch is washed with citric acid. Thereafter, the periphery is passivated by a passivation coating.
摘要翻译：多个半导体器件的接合部形成在共同的晶片中。通过镍，铬，镍，银金属化系统，为每个单个器件对共用晶片的上表面进行金属化。然后将单独的晶片元件与主晶片分离，并且其底表面被真空合金化到钼膨胀板。此后，器件的外围通过研磨而变细，并且周边被热的氢氧化钾蚀刻，而不需要保护上部金属化免受蚀刻。苛性碱蚀刻用柠檬酸洗涤。此后，周边被钝化涂层钝化。

6. 发明授权

US4779125A Semiconductor device and arrangement 失效
标题翻译：半导体器件和布置
公开(公告)号：US4779125A
公开(公告)日：1988-10-18
申请号：US819089
申请日：1986-01-02
申请人： Guido P. T. C. Remmerie , Luc J. L. Van Den Bossche , Daniel F. J. Van De Pol
发明人： Guido P. T. C. Remmerie , Luc J. L. Van Den Bossche , Daniel F. J. Van De Pol
IPC分类号： H01L29/74 , H01L29/745 , H01L29/747 , H01L29/749 , H01L29/08 , H01L29/743
CPC分类号： H01L29/7455 , H01L29/747 , H01L29/749
摘要： The semiconductor device and arrangement include a thyristor switch (T1-T3) with associated turn-on (DM) and turn-off (PM1, PM2) devices. The thy=ristor switch includes a PNP transistor (T1) and one or two NPN transistors (T2, T3) each of which has an emitter constituted by a path of separate regions (115) of N+ material each completely surrounded by P+ material of a zone (110). This path either has a boat shape and partly surrounds and is located at a constant distance of a substantially rectangular zone (109) of P+ material constituting the emitter of the PNP transistor (T1), or has an S-shape and is located at a constant distance of the S-shaped emitter of the PNP transistor (T1).
摘要翻译： PCT No.PCT / EP85 / 00193 Sec。 371日期1986年1月2日第 102（e）日期1986年1月2日PCT提交1985年5月1日PCT公布。公开号WO85 / 05224 日期：1985年11月21日。半导体器件和布置包括具有相关导通（DM）和关断（PM1，PM2）器件的晶闸管开关（T1-T3）。所述晶体管开关包括PNP晶体管（T1）和一个或两个NPN晶体管（T2，T3），每个NPN晶体管具有发射极，由N +材料的分离区域（115）的路径构成，每个区域完全被P +材料包围区域（110）。该路径具有舟状并且部分包围并且位于构成PNP晶体管（T1）的发射极的P +材料的基本矩形区域（109）的恒定距离处，或者具有S形并且位于 PNP晶体管（T1）的S形发射极的恒定距离。

7. 发明授权

US4011579A Semiconductor gate turn-off device 失效
标题翻译：半导体闸极关断装置
公开(公告)号：US4011579A
公开(公告)日：1977-03-08
申请号：US565965
申请日：1975-04-07
申请人： Jearld L. Hutson
发明人： Jearld L. Hutson
IPC分类号： H01L29/423 , H01L29/744 , H01L29/743
CPC分类号： H01L29/42308 , H01L29/744
摘要： The specification discloses a semiconductor switching device which includes heavily doped exterior layers of semiconductor material to provide rapid turn-on and turn-off actions in response to gate signals, while substantially reducing susceptibility to secondary breakdown and the occurrence of significant voltages across the device during a high conductivity mode. A preferred embodiment includes a six layer semiconductor device having a heavily doped P+ exterior layer in contact with an electrode to form an anode terminal, and a heavily doped N+ exterior layer in contact with an electrode to form a cathode terminal. A gate electrode is formed in contact with an intermediate N-type layer adjacent the anode to provide a gate terminal.
摘要翻译：本说明书公开了一种半导体开关器件，其包括重掺杂的半导体材料外层，以响应于栅极信号提供快速的导通和关断动作，同时基本上减少了次级击穿的敏感性以及器件周围的显着电压的出现高导电模式。优选实施例包括具有与电极接触以形成阳极端子的重掺杂P +外部层和与电极接触以形成阴极端子的重掺杂N +外部层的六层半导体器件。栅电极形成为与邻近阳极的中间N型层接触以提供栅极端子。

8. 发明授权

US3959812A High-voltage semiconductor integrated circuit 失效
标题翻译：高压半导体集成电路
公开(公告)号：US3959812A
公开(公告)日：1976-05-25
申请号：US445899
申请日：1974-02-26
申请人： Ichiro Imaizumi
发明人： Ichiro Imaizumi
IPC分类号： H01L21/761 , H01L21/82 , H01L27/06 , H01L29/00 , H01L29/06 , H01L29/743 , H01L27/04 , H01L29/04
CPC分类号： H01L29/0619 , H01L21/761 , H01L21/82 , H01L27/0641 , H01L27/0688 , H01L29/00
摘要： A high-voltage semiconductor integrated circuit consists of an N.sup.- -type substrate, a P.sup.+-type diffusion layer formed on the surface region of the substrate, an N.sup.+-type diffusion layer formed on the P.sup.+-type diffusion layer, and an N.sup.--type epitaxial layer formed on the substrate, forming a high voltage-proof transistor against voltage more than one thousand and several hundred volts. Also, an N.sup.- substrate (collector), N.sup.+-type diffusion layer, and N.sup.+-type diffusion layer, are integrated therewith to form a low-voltage-proof transistor, diode, and PNPN diode in the epitaxial layer so that the entire circuit may take the form of a high voltage-proof power component plus a low voltage-proof control circuit.

9. 发明授权

US3943547A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US3943547A
公开(公告)日：1976-03-09
申请号：US421265
申请日：1973-12-03
申请人： Takahiro Nagano , Tatsuya Kamei , Takuzo Ogawa
发明人： Takahiro Nagano , Tatsuya Kamei , Takuzo Ogawa
IPC分类号： H01L23/31 , H01L29/00 , H01L29/06 , H01L29/743
CPC分类号： H01L29/0661 , H01L23/3157 , H01L29/00 , H01L2924/0002
摘要： A semiconductor device comprising a semiconductor substrate including at least three layers of alternating conductivity between a pair of principal surfaces, the side surface of said semiconductor substrate being formed in pulley-shape and the depth of the valley of the pulley-shape being selected from the most appropriate numerical range related with the dielectric constant of the surrounding medium and the thickness of the semiconductor substrate.
摘要翻译：一种半导体器件，包括半导体衬底，所述半导体衬底在一对主表面之间包括至少三个交替导电层，所述半导体衬底的侧表面形成为滑轮形状，并且所述滑轮形状的谷的深度选自最适合的数值范围与周围介质的介电常数和半导体衬底的厚度有关。

10. 实用新型

JPS576254U 失效
公开(公告)号：JPS576254U
公开(公告)日：1982-01-13
申请号：JP8252780
申请日：1980-06-12
IPC分类号： H01L21/67 , H01L21/52 , H01L21/58 , H01L21/68 , H01L29/41 , H01L29/74 , H01L29/44 , H01L29/743

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