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1. 发明授权

US08217706B2 Method for regulating temperature 有权
标题翻译：调节温度的方法
公开(公告)号：US08217706B2
公开(公告)日：2012-07-10
申请号：US12397444
申请日：2009-03-04
申请人： Alan R. Ball , Stephen P. Robb
发明人： Alan R. Ball , Stephen P. Robb
IPC分类号： H01L35/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/3011 , H03K17/122 , H03K17/145 , H01L2924/00
摘要： A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including a corresponding power FET. When the temperature of the semiconductor substrate near one or more of the power FETs reaches a predetermined value, the corresponding temperature sensing circuit reduces a voltage appearing on the gate of the power FET. The reduced voltage increases the on-resistance of the power FET and channels a portion of its current to others of the plurality of power FETs. The power FET continues operating but with a reduced current flow. When the temperature of the semiconductor substrate falls below the predetermined value, the gate voltage of the power FET is increased to its nominal value.
摘要翻译：一种用于管理集成电路的热性能的方法和电路。并联的温度感测电路和多个功率FET由半导体衬底制造。每个温度感测电路监测半导体衬底的部分或附近的相应功率FET的温度。当一个或多个功率FET附近的半导体衬底的温度达到预定值时，相应的温度感测电路降低了功率FET的栅极上出现的电压。降低的电压增加功率FET的导通电阻，并将其电流的一部分引导到多个功率FET中的其他功率FET。功率FET继续工作，但电流减小。当半导体衬底的温度低于预定值时，功率FET的栅极电压增加到其标称值。

2. 发明授权

US08101969B2 Bi-directional transistor with by-pass path and method therefor 有权
标题翻译：具有旁路的双向晶体管及其方法
公开(公告)号：US08101969B2
公开(公告)日：2012-01-24
申请号：US13023255
申请日：2011-02-08
申请人： Francine Y. Robb , Stephen P. Robb
发明人： Francine Y. Robb , Stephen P. Robb
IPC分类号： H01L29/66
CPC分类号： H03K17/063 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H03K17/687 , H03K2217/0018
摘要： In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.
摘要翻译：在一个实施例中，晶体管被形成为具有第一电流流动路径，以选择性地在两个方向上导通电流通过晶体管，并且具有第二电流流动路径以选择性地在一个方向上导通电流。

3. 发明申请

US20100296210A1 TRANSIENT SUPPRESSION DEVICE AND METHOD THEREFOR 有权
标题翻译：瞬态抑制装置及其方法
公开(公告)号：US20100296210A1
公开(公告)日：2010-11-25
申请号：US12469544
申请日：2009-05-20
申请人： Alan R. Ball , Stephen P. Robb
发明人： Alan R. Ball , Stephen P. Robb
IPC分类号： H02H9/00 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7808 , H01L27/0285 , H01L27/0629 , H01L27/092 , H01L29/7803 , H03K17/302 , H03K2217/0081
摘要： In one embodiment, a semiconductor device to provide protection for electronic circuits, the semiconductor device typically includes a vertical MOS transistor, a reference circuit, and an amplifier. The amplifier amplifies the reference voltage to enable the vertical MOS transistor responsively to a transient event.
摘要翻译：在一个实施例中，提供对电子电路的保护的半导体器件，该半导体器件通常包括垂直MOS晶体管，参考电路和放大器。放大器放大参考电压，以使垂直MOS晶体管响应于瞬态事件。

4. 发明申请

US20100133610A1 METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE 有权
标题翻译：形成集成电力设备和结构的方法
公开(公告)号：US20100133610A1
公开(公告)日：2010-06-03
申请号：US12696816
申请日：2010-01-29
申请人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
发明人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
IPC分类号： H01L27/088 , H01L21/77 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/66734
摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
摘要翻译：在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

5. 发明授权

US07583034B2 LED controller and method therefor 有权
标题翻译： LED控制器及其方法
公开(公告)号：US07583034B2
公开(公告)日：2009-09-01
申请号：US11535177
申请日：2006-09-26
申请人： Alejandro Lara-Ascorra , Stephen P. Robb , Alan R. Ball
发明人： Alejandro Lara-Ascorra , Stephen P. Robb , Alan R. Ball
IPC分类号： G09G3/32
CPC分类号： H05B33/0827
摘要： In one embodiment, a vertical N-channel transistor is coupled in a high side configuration to control a current through an LED. A control circuit operates the vertical N-channel transistor to control a value of the current.
摘要翻译：在一个实施例中，垂直N沟道晶体管以高侧配置耦合以控制通过LED的电流。控制电路操作垂直N沟道晶体管以控制电流的值。

6. 发明授权

US06633063B2 Low voltage transient voltage suppressor and method of making 有权
标题翻译：低压瞬态电压抑制器及其制造方法
公开(公告)号：US06633063B2
公开(公告)日：2003-10-14
申请号：US09849720
申请日：2001-05-04
申请人： Francine Y. Robb , Jeffrey Pearse , David M. Heminger , Stephen P. Robb
发明人： Francine Y. Robb , Jeffrey Pearse , David M. Heminger , Stephen P. Robb
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L27/0623 , H01L29/1087 , H01L29/41741 , H01L29/7801 , H01L29/7802 , H01L29/7813 , H01L29/7818 , H01L29/861
摘要： A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
摘要翻译：使用金属氧化物半导体（MOS）结构和绝缘栅双极晶体管（IGBT）结构来描述提供瞬态电压抑制（TVS）器件的方法。基于MOS的TVS器件提供减少的漏电流，钳位电压在0.5和5伏之间。基于沟槽MOS的TVS器件（ 72 ）提供了增强的增益操作，而器件（ 88 ）提供了顶部漏极联系。基于高增益MOS的TVS器件可以提高对钳位电压变化的控制

7. 发明授权

US06204097B1 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06204097B1
公开(公告)日：2001-03-20
申请号：US09259602
申请日：1999-03-01
申请人： Zheng Shen , Francine Y. Robb , Stephen P. Robb
发明人： Zheng Shen , Francine Y. Robb , Stephen P. Robb
IPC分类号： H01L21332
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0847 , H01L29/1095 , H01L29/456 , H01L29/66333 , H01L29/7395 , H01L29/7802
摘要： A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.
摘要翻译：一种具有端接结构（25）和降低的导通电阻的半导体器件（10）。使用与用于制造有源器件区域（21）的相同的处理步骤来制造端接结构（25）。端接结构（25）和有源器件区（21）通过将沟槽（22,23）蚀刻成漂移层（14）形成。沟槽（22,23）用掺杂的多晶硅沟槽填充材料（24）填充，随后将其平坦化。半导体器件（10）形成在填充有活性区域中的多晶硅沟槽填充材料（24）的沟槽（22）中。填充有端接区域中的多晶硅沟槽填充材料（24）的沟槽（23）用作端接结构。

8. 发明授权

US6166893A Semiconductor load driver circuit and method therefor 有权
标题翻译：半导体负载驱动电路及其方法
公开(公告)号：US6166893A
公开(公告)日：2000-12-26
申请号：US217288
申请日：1998-12-21
申请人： Zheng Shen , Stephen P. Robb
发明人： Zheng Shen , Stephen P. Robb
IPC分类号： H01F7/18 , H03K17/0814 , H02H3/18
CPC分类号： H03K17/08148 , H01F7/1844
摘要： A load driver circuit (10) includes an output driver (11) suitable for driving an inductive load (13). An output clamp circuit (15) clamps the output (12) to a high voltage during turn-off of the output driver (11). An open load detect circuit (26) clamps the output (12) to a lower voltage when the load (13) has an open circuit fault. A power fault voltage detect circuit (28) clamps the output (12) to another low voltage during a power fault condition.
摘要翻译：负载驱动器电路（10）包括适于驱动感性负载（13）的输出驱动器（11）。输出钳位电路（15）在输出驱动器（11）的关断期间将输出（12）钳位到高电压。当负载（13）具有开路故障时，开路负载检测电路（26）将输出（12）钳位到较低的电压。电源故障电压检测电路（28）在电源故障状态期间将输出（12）钳位到另一低电压。

9. 发明授权

US06160691A Method of driving a load and semiconductor load driver circuit therefor 有权
标题翻译：驱动负载和半导体负载驱动电路的方法
公开(公告)号：US06160691A
公开(公告)日：2000-12-12
申请号：US216763
申请日：1998-12-21
申请人： Zheng Shen , Stephen P. Robb
发明人： Zheng Shen , Stephen P. Robb
IPC分类号： H03K17/082 , H02H3/18
CPC分类号： H03K17/0828
摘要： A load driver circuit (10) includes an output driver (11) suitable for driving an inductive load (13). An output clamp circuit (15) clamps the output (12) to a high voltage during turn-off of the output driver (11). An open load detect circuit (26) clamps the output (12) to a lower voltage when the load (13) has an open circuit fault. A power fault voltage detect circuit (28) clamps the output (12) to another low voltage during a power fault condition.
摘要翻译：负载驱动器电路（10）包括适于驱动感性负载（13）的输出驱动器（11）。输出钳位电路（15）在输出驱动器（11）的关断期间将输出（12）钳位到高电压。当负载（13）具有开路故障时，开路负载检测电路（26）将输出（12）钳位到较低的电压。电源故障电压检测电路（28）在电源故障状态期间将输出（12）钳位到另一低电压。

10. 发明授权

US5747371A Method of manufacturing vertical MOSFET 失效
标题翻译：制造垂直MOSFET的方法
公开(公告)号：US5747371A
公开(公告)日：1998-05-05
申请号：US684802
申请日：1996-07-22
申请人： Francine Y. Robb , Stephen P. Robb , Jean-Michel Reynes , Li-Hsin Chang
发明人： Francine Y. Robb , Stephen P. Robb , Jean-Michel Reynes , Li-Hsin Chang
IPC分类号： H01L21/336 , H01L29/32 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/32 , H01L29/7802 , Y10S438/904
摘要： A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.
摘要翻译：半导体器件包括衬底（11），衬底（11）中的第一区域（21），其中第一区域（21）具有第一导电类型，在衬底（11）中的第二区域（22），其中第二区域区域（22）与第一区域（21）相邻，并且其中第二区域（22）具有不同于第一导电类型的第二导电类型，以及在衬底（11）中的第三区域（24），其中第三区域（24）与第一和第二区域（21,22）重叠，并且其中第三区域（24）具有损坏的晶体结构。

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