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1. 发明申请

WO2020211322A1 UNIFIED SEMICONDUCTOR DEVICES HAVING PROGRAMMABLE LOGIC DEVICE AND HETEROGENEOUS MEMORIES AND METHODS FOR FORMING THE SAME 审中-公开
公开(公告)号：WO2020211322A1
公开(公告)日：2020-10-22
申请号：PCT/CN2019/113238
申请日：2019-10-25
申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.
发明人： LIU, Jun , CHEN, Weihua
IPC分类号： H01L27/1157 , H01L25/18 , H01L27/108 , H01L21/60 , H01L21/78 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/48091 , H01L2224/80895 , H01L2224/80896 , H01L2224/82 , H01L2224/95 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06562 , H01L24/08 , H01L24/80 , H01L24/82 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L27/10897 , H01L27/1116 , H01L27/11573 , H01L2924/181
摘要： A semiconductor device (700) includes a first semiconductor structure (702) including NAND memory cells and a first bonding layer (730) including first bonding contacts (732). The semiconductor device (700) also includes a second semiconductor structure (704) including DRAM cells and a second bonding layer (750) including second bonding contacts (752). The semiconductor device (700) also includes a third semiconductor structure (706) including a programmable logic device (716) and a third bonding layer (726) including third bonding contacts (728). The semiconductor device (700) further includes a first bonding interface (708) between the first and third bonding layers, and a second bonding interface (710) between the second and third bonding layers. The first bonding contacts (732) are in contact with a first set of the third bonding contacts (728) at the first bonding interface (708). The second bonding contacts (752) are in contact with a second set of the third bonding contacts (728) at the second bonding interface (710). The first and second bonding interfaces are in a same plane.

2. 发明申请

WO2022043033A1 ELECTRONIC DEVICE, PACKAGE AND SEMICONDUCTOR CHIP THEREFORE 审中-公开
公开(公告)号：WO2022043033A1
公开(公告)日：2022-03-03
申请号：PCT/EP2021/072081
申请日：2021-08-06
申请人： HITACHI ENERGY SWITZERLAND AG [CH]/[CH]
发明人： STIASNY, Thomas , WIKSTROEM, Tobias
IPC分类号： H01L21/603 , H01L23/051 , H01L25/10 , H01L2224/03602 , H01L2224/0361 , H01L2224/04 , H01L2224/04042 , H01L2224/05011 , H01L2224/05012 , H01L2224/05551 , H01L2224/05552 , H01L2224/05558 , H01L2224/05624 , H01L2224/0603 , H01L2224/06051 , H01L2224/06181 , H01L2224/48091 , H01L2224/73201 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/72 , H01L24/73 , H01L25/117
摘要： An electronic device (1) comprises a semiconductor chip (2) having an electrical contact metallization (3), and a package (4) having an electrical contact disc (5). The electrical contact metallization (3) and the electrical contact disc (5) are in direct contact on a contact face (45) so that the semiconductor chip (2) is electrically connected with the package (4). At the contact face (45), at least one of the electrical contact metallization (3) and the electrical contact disc (5) comprises a geometric structuring (6) (a surface pattern) fashioned as at least one recessed area. A mean roughness of a top face (50) of the electrical contact disc (5) facing the electrical contact metallization (3) may be between 0.2 pm and 1 pm, wherein, because of the mean roughness, the top face (50) is configured to penetrate an oxide layer (31) of the electrical contact metallization (3) at the contact face (45) (e.g., native oxide on an aluminum metallization (3) ). The electrical contact metallization (3) may be of multilayer fashion and comprise at least one interrupted sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) being located at the contact face (45), wherein the at least one interrupted sub-layer (33) and the at least one continuous sub-layer (34) may be of the same material or of different materials, but have different thicknesses. All of the electrical contact metallization (3) and/or of the electrical contact disc (5) may be configured to be on the same electric potential. The geometric structuring (6) may consist of or comprise at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, honeycomb and may comprise interruptions. The semiconductor chip (2) may comprise a further electrical contact metallization (7) having an even and smooth further contact face (70), wherein, seen in top view, an overall size of the further contact face (70) is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and by at most a factor of 5, and wherein, because of the geometric structuring (6), at the contact face (45) an effective size of the electrical contact metallization (3) is the same as the overall size of the further contact face (70), with a tolerance of at most a factor of 1.2, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) may be located at opposite main sides of the semiconductor chip (2) and the semiconductor chip (2) is configured to be electrically contacted with a contact force of at least 0.3 kN/cm and of at most 2 kN/cm. The package (4) may comprise an electrically insulating jacket (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disc (5) as well as the metal plate (42) are arranged in the jacket (41) and are aligned in parallel with each other, wherein, seen in top view onto the contact face (45), sizes of the semiconductor chip (2) and the electrical contact disc (5) differ from each other by at most a factor of 1.3, and wherein the electrical contact disc (5) is located between the semiconductor chip (2) and the contact plate (42). The semiconductor chip (2), the electrical contact disc (5) and the optional contact plate (42) can be of circular shape seen in top view. The electronic device (1) may be a press pack power semiconductor device. The pressure at a given contact force is increased in the electronic device (1) by reducing the overall contact area, that is, a contact face (45) between the electrical contact metallization (3) of the semiconductor chip (2) and the electrical contact disc (5) of the package (4), to form a reliable and stable dry interface electric contact and avoid 'too low pressure1 effects, for example: for an anode side metallization of an IGCT or of an GTO, as the clamping force is typically limited for by the mechanical stability of the cathode side metallization which is in total significantly lower in contact area and more fragile due to the segmentation of a high metal stack; for a metallization of a free-floating side of a bonded diode used at low clamping forces, for example, when clamped with an IGCT - for a free-floating anode side, the probability of electromigration may be higher; or for an anode and cathode side metallization of a free-floating diode or of a free-floating plus diode clamped at relatively low pressures.

3. 发明申请

WO2021140572A1 半導体装置および電力変換装置审中-公开
公开(公告)号：WO2021140572A1
公开(公告)日：2021-07-15
申请号：PCT/JP2020/000192
申请日：2020-01-07
申请人：三菱電機株式会社
发明人：堀口　剛司 , 椋木　康滋
IPC分类号： H01L23/58 , H01L25/07 , H01L21/60 , H01L2224/48091 , H01L2224/49111 , H01L2224/73265 , H01L2924/19107
摘要：半導体装置（１００）は、第１電極（１１）と第２電極（１２）とを有する半導体素子（１）と、第１電極（１１）と接合部を介して電気的に接続された第１導電体（７）と、第１方向（Ａ）において第１導電体（７）と絶縁体（８）を挟むように積層された第２導電体（９）と、第２導電体（９）上に配置されかつ第２導電体（９）と電気的に接続されている第１端子（３）と、第２導電体（９）上に配置されている第２端子（４）と、第２電極（１２）と第２端子（４）とを電気的に接続する複数の配線部材（５）とを備える。

4. 发明申请

WO2022269772A1 バンプ形成装置、バンプ形成方法及びバンプ形成プログラム审中-公开
公开(公告)号：WO2022269772A1
公开(公告)日：2022-12-29
申请号：PCT/JP2021/023669
申请日：2021-06-22
申请人：株式会社新川
发明人：田中　清貴
IPC分类号： H01L21/60 , H01L2224/48091 , H01L2224/48479 , H01L2224/4848 , H01L2224/48485 , H01L2224/78 , H01L2224/78301 , H01L2224/85051
摘要：バンプ形成装置（１）は、ボンディングツール（１５）と、ボンディング制御部（１０）とを備え、ボンディング制御部は、圧着工程（Ｓ１４）と、繰出工程（Ｓ１５）と、押圧工程（Ｓ１６）と、切断工程（Ｓ１７）と、を実行するように構成され、ワイヤ（ｗ）に関する第１パラメータと、ボンディングツール（１５）の形状に関する第２パラメータとに基づいて、ボンディングツール（１５）の軌道のうち少なくとも繰出工程（Ｓ１５）における軌道が決定される。

5. 发明申请

WO2022264298A1 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：WO2022264298A1
公开(公告)日：2022-12-22
申请号：PCT/JP2021/022790
申请日：2021-06-16
申请人：三菱電機株式会社
发明人：山竹　厚 , 塩田　裕基
IPC分类号： H01L23/28 , H01L25/07 , H01L25/18 , H01L2224/48091 , H01L2224/92247 , H01L2924/19107
摘要：絶縁層（３）を介して半導体素子（５）が第一の面に搭載されたベース板（２）と、ベース板（２）に接着剤（７）を介して接着されたケース（６）と、を備えた半導体装置（１）であって、ケース（６）は、鉛直方向に伸びる延伸部位（６１）と延伸部位の下端よりも上方で内側に突出した突出部位（６２）とを有し、突出部位（６１）の下面（６ａ）と前記ベース板（２）の第一の面の周辺部とが接し、突出部位（６１）の下面（６ｃ）から繋がり延伸部位（６１）から突出した突起部（１４）がベース板（２）の側面（２ａ）と離間して設けられ、ベース板（２）の側面（２ａ）と延伸部位（６１）との間が接着剤（７）で充填されている。

6. 发明申请

WO2015069184A1 A GUARD STRUCTURE FOR SIGNAL ISOLATION 审中-公开
公开(公告)号：WO2015069184A1
公开(公告)日：2015-05-14
申请号：PCT/SG2014/000470
申请日：2014-10-07
申请人： THALES SOLUTIONS ASIA PTE LTD. , CNRS - CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (EPST) , NANYANG TECHNOLOGICAL UNIVERSITY
发明人： TAN, Dunlin , YU, Jong Jen , HEE, David , TAY, Beng Kang , BAILLARGEAT, Dominique
IPC分类号： H01L23/552 , H01L23/04 , H01L23/498 , H01L23/66 , H01L25/065 , H01L25/16 , H05K9/00 , B82Y10/00 , H01L2223/6616 , H01L2223/6683 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32165 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L23/3677 , H01L23/373 , H01L23/49827 , H01L23/49838 , H01L23/49877 , H01L23/5384 , H01L23/5385 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L29/0676 , H01L29/413 , H01L2924/00014 , H01L2924/01006 , H01L2924/14 , H01L2924/1421 , H01L2924/1423 , H01L2924/157 , H01L2924/3025 , H05K9/0022
摘要： A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

7. 发明申请

WO2022002464A1 LEISTUNGSMODUL MIT MINDESTENS DREI LEISTUNGSEINHEITEN 审中-公开
公开(公告)号：WO2022002464A1
公开(公告)日：2022-01-06
申请号：PCT/EP2021/061669
申请日：2021-05-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： SCHMENGER, Jens , KÖGLER, Roman , LUFT, Alexander , NAMYSLO, Lutz , ROPPELT, Bernd , SCHWINN, Thomas
IPC分类号： H01L23/467 , H01L23/373 , H01L25/07 , H01L21/48 , H01L23/498 , H01L23/538 , H01L21/4882 , H01L2224/06181 , H01L2224/29111 , H01L2224/2919 , H01L2224/32227 , H01L2224/40227 , H01L2224/45014 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8384 , H01L23/3735 , H01L23/49811 , H01L23/5385 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/48 , H01L25/072 , H01L25/115 , H01L2924/1203 , H01L2924/1304 , H01L2924/19107
摘要： Die Erfindung betrifft ein Leistungsmodul (2) mit mindestens zwei Leistungseinheiten (4), welche jeweils mindestens einen Leistungshalbleiter (6) und ein Substrat (8) umfassen. Um den erforderlichen Bauraum des Leistungsmoduls zu verringern und eine Entwärmung zu verbessern, wird vorgeschlagen, dass der jeweils mindestens eine Leistungshalbleiter (6), insbesondere stoffschlüssig, mit dem jeweiligen Substrat (8) verbunden ist, wobei die Substrate (8) der mindestens zwei Leistungseinheiten (4) jeweils unmittelbar stoffschlüssig mit einer Oberfläche (24) eines gemeinsamen Kühlkörpers (26) verbunden sind.

8. 发明申请

WO2021202038A1 SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING 审中-公开
公开(公告)号：WO2021202038A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/020549
申请日：2021-03-02
申请人： MICRON TECHNOLOGY, INC.
发明人： JENSEN, Travis, M. , HEMBREE, David, R.
IPC分类号： H01L25/065 , H01L23/485 , H01L23/525 , H01L21/60 , H01L2224/0235 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/131 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06586 , H01L24/02 , H01L25/0657 , H01L25/50 , H01L2924/15311
摘要： Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

9. 发明申请

WO2021074050A2 SOCKEL FÜR EIN GEHÄUSE MIT EINER ELEKTRONISCHEN KOMPONENTE ZUR HOCHFREQUENZ-SIGNALÜBERTRAGUNG 审中-公开
公开(公告)号：WO2021074050A2
公开(公告)日：2021-04-22
申请号：PCT/EP2020/078542
申请日：2020-10-12
申请人： SCHOTT AG
发明人： DRÖGEMÜLLER, Karsten , AOWUDOMSUK, Artit
IPC分类号： H01S5/062 , H01S5/02212 , H01S5/02345 , H01L23/00 , H01L23/045 , H01S5/024 , H01S5/12 , H01L2224/131 , H01L2224/13144 , H01L2224/16227 , H01L2224/291 , H01L2224/29144 , H01L2224/32225 , H01L2224/48091 , H01L2224/48159 , H01L2224/48165 , H01L2224/48227 , H01L2224/49113 , H01L2224/73265 , H01L2224/92247 , H01L23/38 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2924/12042 , H01S5/00 , H01S5/0231 , H01S5/02325 , H01S5/02415 , H01S5/06226
摘要： Der Erfindung liegt die Aufgabe zugrunde, einen Sockel mit einer verbesserten Kühlung für elektronische Bauelemente zur Hochfrequenz-Signalübertragung bereitzustellen. Dazu ist ein Sockel (1) für ein elektronisches Bauelement (10) zur Hochfrequenz-Datenübertragung vorgesehen, wobei - der Sockel einen metallischen Grundkörper (5) mit mehreren elektrischen Durchführungen (7) umfasst, und wobei der Sockel (1) - ein thermoelektrisches Kühlelement (9) umfasst, welches eine auf dem Grundkörper aufliegende Seite (11) und eine gegenüberliegende Seite (13) zur Anbringung der elektronischen Komponente (3) aufweist, wobei - auf der Seite (13) zur Anbringung der elektronischen Komponente (3) eine Hochfrequenz-Leitung (12) zur elektronischen Komponente (3) mit einem Erdleiter vorgesehen ist, der mit dem metallischen Grundkörper (5) elektrisch verbunden ist, und wobei die elektrische Verbindung zum metallischen Grundkörper (5) ein Tellurid- Element umfasst.

10. 发明申请

WO2023274629A1 HOLDER AND MOUNTING METHOD FOR QUANTUM DEVICE 审中-公开
公开(公告)号：WO2023274629A1
公开(公告)日：2023-01-05
申请号：PCT/EP2022/063858
申请日：2022-05-23
申请人： QDEVIL APS
发明人： ANDRESEN, Søren , KANN, Peter, Ulrik , VON SOOSTEN, Merlin
IPC分类号： H01L23/32 , G06N10/40 , G01R31/28 , H01L2223/6611 , H01L2223/6627 , H01L2223/6677 , H01L2224/13101 , H01L2224/16225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73265 , H01L23/552 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2924/00014 , H01L2924/0781 , H01L2924/15156 , H01L2924/16152 , H01L2924/3025
摘要： A sample holder (10) for a quantum device (16) comprises a first portion (12b) comprising a first cavity (14b), a second portion (12a) comprising a second cavity (14a), first fixing elements comprising a printed circuit board (18) including electrical conductors and/or wave guides, and second fixing elements (24) configured to fix the first and second portions to each other. The quantum device, particularly comprising one or more qubits based on superconducting junction devices or single electron devices, is provided over and covering at least part of the cavities, is fixed to the first portion by the first fixing elements, and the electrical conductors and/or wave guides are connected to the quantum device and extend to the outside.

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