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1. 发明申请

US20040238916A1 Edge intensive antifuse and method for making the same 有权
公开(公告)号：US20040238916A1
公开(公告)日：2004-12-02
申请号：US10882969
申请日：2004-06-30
发明人： Jigish D. Trivedi
IPC分类号： H01L021/82 , H01L029/00
CPC分类号： H01L23/5252 , G11C17/16 , H01L23/5254 , H01L27/101 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L2924/0002 , Y10T29/49016 , Y10T29/49107 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49155 , Y10T29/4916 , Y10T29/49165 , H01L2924/00
摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

2. 发明申请

US20040237118A1 Method for displaying an interactive game having a pre-determined outcome 有权
公开(公告)号：US20040237118A1
公开(公告)日：2004-11-25
申请号：US10864784
申请日：2004-06-08
发明人： Norman H. Millerschone
IPC分类号： H04N007/173 , A63F013/00 , G06F019/00 , G06F017/00 , H04N007/16 , H01L021/82 , G09B019/22 , A63F009/24
CPC分类号： G07F17/32 , A63F13/10
摘要： An interactive game having a pre-determined outcome (e.g., a game of finite poker) that displays an initial hand of cards, receives a player-specified designation as to which cards are to held and which are to be discarded, and then displays an intermediate hand generated in accordance with the player-specified designation. Then a final hand is shown, and in those cases where the player-specified designation (Hold/Discard) is inconsistent with a transition from the intermediate hand to the final hand, an entertaining display is shown, such as a sequence of alternative playing cards. In some cases, the initial hand is a winning hand according to a predetermined payout schedule, and the final hand is a winning hand with a higher payout than the initial hand according to the same payout schedule. The disclosed methods can be used with other games, including reel-type games.

3. 发明申请

US20040224443A1 METAL PROGRAMMABLE INTEGRATED CIRCUIT CAPABLE OF UTILIZING A PLURALITY OF CLOCK SOURCES AND CAPABLE OF ELIMINATING CLOCK SKEW 有权
标题翻译：金属可编程集成电路，可以利用多个时钟源，并能够消除时钟轴
公开(公告)号：US20040224443A1
公开(公告)日：2004-11-11
申请号：US10249745
申请日：2003-05-05
发明人： Hsin-Shih Wang , Shang-Jyh Shieh
IPC分类号： H01L021/82
CPC分类号： G06F1/10 , H01L27/11803
摘要： A method for forming a metal programmable integrated circuit that can use a plurality of clock sources and balance clock skew. The integrated circuit has a semiconductor body. The method includes step (a) used for forming a plurality of basic units on the semiconductor body wherein each basic unit has at least a logic module, at least a driving module, and at least a storage module, and step (b) used for forming a metal layer for programming the logic module to be able to perform logic operations, programming the driving module to able to drive an input signal inputted into the driving module, and programming the storage module to be able to store data after performing step (a).
摘要翻译：一种用于形成可以使用多个时钟源并平衡时钟偏移的金属可编程集成电路的方法。该集成电路具有半导体本体。该方法包括用于在半导体本体上形成多个基本单元的步骤（a），其中每个基本单元至少具有一个逻辑模块，至少一个驱动模块和至少一个存储模块，以及步骤（b）形成用于对所述逻辑模块进行编程以便能够执行逻辑操作的金属层，对所述驱动模块进行编程以能够驱动输入到所述驱动模块的输入信号，以及对所述存储模块进行编程，以便能够在执行步骤（a ）。

4. 发明申请

US20040217483A1 Semiconductor device and method for fabricating the semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20040217483A1
公开(公告)日：2004-11-04
申请号：US10836143
申请日：2004-04-30
申请人： Infineon Technologies AG
发明人： Harry Hedler , Roland Irsigler , Thorsten Meyer
IPC分类号： H01L021/82 , H01L023/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/73265 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/00015 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/85399 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/0401 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.
摘要翻译：半导体器件具有半导体衬底，至少第一和第二重新布线装置在半导体衬底的第一表面上，用于提供半导体衬底的电接触连接，以及从第一表面到第二表面的渐缩连续的开口第二，半导体衬底的相对表面。至少第三和第四重新布线装置设置在半导体衬底的第二表面上，并且在开口的侧面区域上形成图案化金属化，用于第一和第二重新布线装置的单独接触连接。

5. 发明申请

US20040217439A1 Fuse and method for forming 失效
标题翻译：保险丝和成型方法
公开(公告)号：US20040217439A1
公开(公告)日：2004-11-04
申请号：US10425275
申请日：2003-04-29
发明人： Chi Nan Brian Li , Alexander B. Hoefler , Der-Gao Lin
IPC分类号： H01L021/82 , H01L029/00 , H01L021/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.
摘要翻译：有源保险丝包括用于形成可变电阻器（106）和选择晶体管（110）的有源熔丝几何形状（120）。在一个实施例中，有源熔丝几何形状形成在半导体衬底（140）的有源区（160）的一部分中，并且选择栅极（124）设置在有源熔丝几何体的端部（123）上方，形成用于编程有源保险丝的整体选择晶体管（110）。在有源区域内使用共享的有源保险丝几何形状允许减少面积要求和改进的感测裕度。

6. 发明申请

US20040178456A1 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20040178456A1
公开(公告)日：2004-09-16
申请号：US10797754
申请日：2004-03-09
申请人： Samsung Electronics Co., Ltd.
发明人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
IPC分类号： H01L021/82 , H01L029/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328
摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.
摘要翻译：非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。栅极间电介质的宽度比底栅图案的宽度窄。

7. 发明申请

US20040159907A1 Semiconductor integrated circuit including anti-fuse and method for manufacturing the same 有权
标题翻译：包括反熔丝的半导体集成电路及其制造方法
公开(公告)号：US20040159907A1
公开(公告)日：2004-08-19
申请号：US10773213
申请日：2004-02-09
申请人： KAWASAKI MICROELECTRONICS, INC.
发明人： Isamu Kuno , Tomoharu Katagiri
IPC分类号： H01L021/82 , H01L029/00
CPC分类号： H01L21/76202 , G11C17/18 , H01L23/5252 , H01L27/0617 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.
摘要翻译：通过在半导体衬底的表面上形成包括掩埋在器件形成区域的表面中的绝缘材料层的隔离区域，并且通过在隔离区域的两侧形成扩散区域来制造反熔丝，到各个扩散区域。反熔丝最初处于非导通状态，并通过简单的写入电路被编程为处于永久导通状态。

8. 发明申请

US20040157417A1 Methods to form a memory cell with metal-rich metal chalcogenide 失效
标题翻译：用金属富金属硫族化物形成记忆电池的方法
公开(公告)号：US20040157417A1
公开(公告)日：2004-08-12
申请号：US10769787
申请日：2004-02-03
发明人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
IPC分类号： H01L021/04 , H01L021/8234 , H01L021/82 , H01L021/8244
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/085 , H01L45/143 , H01L45/1641
摘要： The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.
摘要翻译：本发明涉及电阻可变材料单元或可编程金属化单元的制造。本文所述的方法可形成金属富金属硫族化物，例如富银硒化银。有利的是，该方法可以形成富含金属的金属硫属元素化物，而不需要使用光致激发技术，而不会直接沉积金属。例如，该过程可以从硒化银中除去硒。该方法的一个实施方案是将氧沉积到硒化银以形成氧化硒。然后通过退火除去氧化硒，这导致富银银硒化银。有利的是，该方法可以将银掺杂到各种材料中，包括非透明材料，具有相对高的均匀性和相对精确的控制。

9. 发明申请

US20040135230A1 Self-passivating Cu laser fuse 失效
标题翻译：自钝化铜激光保险丝
公开(公告)号：US20040135230A1
公开(公告)日：2004-07-15
申请号：US10745263
申请日：2003-12-23
发明人： Hans-Joachim Barth
IPC分类号： H01L021/82 , H01L029/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising: a metallization-line; a liner separating the metallization line and a combination Cu-alloy seed layer and a pure Cu layer; a dielectric surrounding the liner; and a dielectric cap disposed over the surrounding dielectric, the liner and the combination Cu-alloy seed layer and pure Cu layer; the laser fuse being characterized after laser energizing by passivation areas: a) on the open Cu-fuse surface; and b) in the interfaces between: (i) the Cu-alloy seed layer and the liners and dielectric; and (ii) between the pure Cu layer and the dielectric cap.
摘要翻译：在集成电路结构中，改进包括自钝化铜激光熔丝，其特征在于抗氧化和腐蚀，并且在Cu和金属化线之间的界面中改善粘合性，并且通过激励激光器熔化熔丝后的Cu和介电帽所述保险丝包括：金属化线; 分离金属化线和组合的Cu合金种子层和纯Cu层的衬里; 围绕衬套的电介质; 以及设置在周围电介质，衬垫和组合Cu合金晶种层和纯Cu层上的电介质盖; 激光熔丝的特征在于钝化区域激光激励后：a）在开放的Cu熔丝表面上; 和b）在以下界面中：（i）Cu合金种子层和衬垫和电介质; 和（ii）在纯Cu层和电介质盖之间。

10. 发明申请

US20040101996A1 Interconnection structure and method for designing the same 失效
公开(公告)号：US20040101996A1
公开(公告)日：2004-05-27
申请号：US10703605
申请日：2003-11-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Chihiro Hyoto , Kiyoshi Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
IPC分类号： H01L021/82
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.

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