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1. 发明申请

US20020094641A1 Method for fabricating floating gate 有权
公开(公告)号：US20020094641A1
公开(公告)日：2002-07-18
申请号：US10053792
申请日：2002-01-18
申请人： Samsung Electronics Co., Ltd.
发明人： Kwang-Shik Shin , Sung-Nam Chang , Jae-Woo Kim
IPC分类号： H01L021/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask. With the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.

2. 发明申请

US20040175924A1 Semiconductor device having resistor and method of fabricating the same 审中-公开
标题翻译：具有电阻器的半导体器件及其制造方法
公开(公告)号：US20040175924A1
公开(公告)日：2004-09-09
申请号：US10792439
申请日：2004-03-02
申请人： Samsung Electronics Co., Ltd.
发明人： Eun-Young Choi , Sung-Nam Chang , Won-Hong Lee , Kwang-Shik Shin
IPC分类号： H01L031/20
CPC分类号： H01L27/11524 , H01G4/228 , H01G4/33 , H01L27/0629 , H01L27/0802 , H01L27/115 , H01L27/11521 , H01L28/24
摘要： A method according to some embodiments of the invention includes sequentially forming first and second conductive layers, patterning the second conductive layer to form second conductive patterns, and forming a mask pattern connecting the second conductive patterns. Using the mask pattern and the second conductive patterns as an etching mask, the first conductive layer is etched to form a first conductive pattern electrically connecting the second conductive patterns. Before the second conductive layer is formed, a gate interlayer insulating layer including at least two openings exposing a top surface of the first conductive layer may be formed. The second conductive patterns are in contact with top surfaces of the first conductive pattern. During formation of the second conductive patterns, a dummy pattern may be formed on the gate interlayer insulating layer and spaced apart from the second conductive patterns.
摘要翻译：根据本发明的一些实施例的方法包括顺序地形成第一和第二导电层，图案化第二导电层以形成第二导电图案，以及形成连接第二导电图案的掩模图案。使用掩模图案和第二导电图案作为蚀刻掩模，蚀刻第一导电层以形成电连接第二导电图案的第一导电图案。在形成第二导电层之前，可以形成包括暴露第一导电层的顶表面的至少两个开口的栅极层间绝缘层。第二导电图案与第一导电图案的顶表面接触。在形成第二导电图案期间，可以在栅极层间绝缘层上形成虚拟图案并且与第二导电图案间隔开。

3. 发明申请

US20020187609A1 Non-volatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20020187609A1
公开(公告)日：2002-12-12
申请号：US10160875
申请日：2002-05-30
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-Chan Kim , Sung-Nam Chang
IPC分类号： H01L021/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： Non-volatile memory devices and fabrication methods thereof are provided. The device includes a plurality of isolation layers formed at a semiconductor device, a plurality of stacked gates crossing over an active region between the isolation layers, and an oxidation barrier layer covering the stacked gate. Each of the stacked gates has a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the control gate electrode and the floating gate. Also, the inter-gate dielectric layer has a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked. The oxidation barrier layer is formed prior to a subsequent thermal oxidation process for curing etch damage that occurs during formation of the stacked gates.
摘要翻译：提供非易失性存储器件及其制造方法。该器件包括形成在半导体器件上的多个隔离层，跨过隔离层之间的有源区域的多个层叠栅极和覆盖堆叠栅极的氧化阻挡层。层叠栅极中的每一个具有跨越有源区域的控制栅极电极，插入在控制栅电极和有源区域之间的浮置栅极以及介于控制栅极电极和浮置栅极之间的栅极间电介质层。此外，栅极间电介质层具有依次层叠的底部电介质层，中间电介质层和顶部电介质层。在随后的热氧化过程之前形成氧化阻挡层，用于固化在层叠栅极形成期间发生的蚀刻损伤。

4. 发明申请

US20040178456A1 Non-volatile memory device and fabricating method thereof 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20040178456A1
公开(公告)日：2004-09-16
申请号：US10797754
申请日：2004-03-09
申请人： Samsung Electronics Co., Ltd.
发明人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
IPC分类号： H01L021/82 , H01L029/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328
摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.
摘要翻译：非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。栅极间电介质的宽度比底栅图案的宽度窄。

5. 发明申请

US20030127682A1 Non-volatile memory device having improved coupling ratio uniformity 审中-公开
标题翻译：具有改善的耦合比均匀性的非易失性存储器件
公开(公告)号：US20030127682A1
公开(公告)日：2003-07-10
申请号：US10222109
申请日：2002-08-16
申请人： Samsung Electronics Co., Ltd
发明人： Hun-Kook Lee , Sung-Nam Chang , Sung-Hoi Hur
IPC分类号： H01L029/788
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A NAND-type flash memory device is provided. The flash memory device comprises a plurality of word line patterns formed on the substrate. The total number of the word line patterns is N. The word line patterns are disposed parallel to a string selection line pattern. The word line patterns are disposed between the ground selection line pattern and the string selection line pattern in plan view, and comprises a first word line pattern, a Nth word line pattern and intermediate word line patterns. The first word line pattern is adjacent to the string selection line pattern. The Nth word line pattern is adjacent to the ground selection line pattern. The intermediate word line patterns are disposed between the first and Nth word line patterns in plan view. The first and Nth word line patterns are wider than the intermediate word line patterns.
摘要翻译：提供NAND型闪速存储器件。闪存器件包括形成在衬底上的多个字线图案。字线图案的总数为N.字线图案平行于字符串选择线图案设置。字线图案在平面图中设置在地选择线图案和串选择线图案之间，并且包括第一字线图案，第N字线图案和中间字线图案。第一个字线图案与字符串选择线图案相邻。第N个字线图案与地选择线图案相邻。中间字线图案在平面图中设置在第一和第N字线图案之间。第一和第N字线图案比中间字线图案宽。

6. 发明申请

US20020080659A1 Highly integrated non-volatile memory cell array having a high program speed 有权
标题翻译：具有高程序速度的高度集成的非易失性存储单元阵列
公开(公告)号：US20020080659A1
公开(公告)日：2002-06-27
申请号：US10001460
申请日：2001-10-29
申请人： Samsung Electronics Co., Ltd.
发明人： Kwang-Shik Shin , Kyu-Charn Park , Sung-Nam Chang , Jung-Dal Choi , Won-Hong Lee
IPC分类号： G11C007/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.
摘要翻译：具有第二浮动栅极的非易失性存储单元阵列具有窄的宽度，高的高度和倾斜的侧壁。由于光刻和蚀刻工艺引起的临界尺寸误差降低。存储器单元之间的耦合比率的差异很小，从而在编程和/或擦除期间提高速度。可以设计具有比使用光刻工艺获得的第二浮动栅极更窄的临界尺寸的第二浮动栅极，由此形成高度集成的非易失性存储单元阵列。

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