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1. 发明申请

US20040038488A1 SOI device having increased reliability and reduced free floating body effects 失效
标题翻译： SOI器件具有增加的可靠性和减少的自由浮体效应
公开(公告)号：US20040038488A1
公开(公告)日：2004-02-26
申请号：US10226283
申请日：2002-08-23
发明人： Chandra Mouli
IPC分类号： H01L021/331 , H01L021/00 , H01L021/479 , H01L021/326 , H01L021/84 , H01L021/336
CPC分类号： H01L27/10873 , H01L21/3003 , H01L21/326 , H01L21/84 , H01L21/86 , H01L27/10805 , H01L27/12 , H01L27/1203 , H01L29/66772 , H01L29/78609 , H01L29/78612
摘要： The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.
摘要翻译：本发明提供了一种新的方法，用于在氘退火之前通过在氘退火之前预加压所制造的器件来增加在氘钝化退火期间掺入晶体管器件陷阱位置的氘的量。本发明的方法同样适用于SOI和CMOS技术。结果，在工艺流程中在氘退火期间掺入更多的氘可以减少不期望的捕集点的数量。

2. 发明申请

US20030017676A1 Operating method for a semiconductor component 有权
标题翻译：半导体元件的操作方法
公开(公告)号：US20030017676A1
公开(公告)日：2003-01-23
申请号：US10200067
申请日：2002-07-19
发明人： Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L021/20 , H01L021/326
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).
摘要翻译：本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体元件在其具有第一差分电阻（Rdiff1）的电流/电压范围内可逆地操作，直到对应于高电压限制值（Vt）的电流限制值（It），并且在当前值大于这具有小于第一差分电阻（Rdiff1）的第二差分电阻（Rdiff2）。

3. 发明申请

US20010050407A1 Anti-fuse structure and method of writing and reading in integrated circuits 有权
标题翻译：集成电路中的反熔丝结构和写入和读取方法
公开(公告)号：US20010050407A1
公开(公告)日：2001-12-13
申请号：US09873035
申请日：2001-06-02
发明人： Tito Gelsomini , Kemal Tamer San
IPC分类号： H01L021/82 , H01L021/326 , H01L021/479 , H01L029/00
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.
摘要翻译：嵌入在集成电路（IC）中的信息写入寄存器由形成在嵌套在n阱中的隔离p阱中的多个可独立寻址的门控元件构成。位于p阱上的栅极位于几何形状上的绝缘体上，使得其在施加过应力电压脉冲时局部易于导电，由此二进制信息可以被永久地编码到写寄存器中。过应力电压脉冲施加在栅极和p阱之间，并且当具有相反极性和较短持续时间的p阱脉冲叠加预定极性和持续时间的写使能脉冲时产生。

4. 发明申请

US20010041460A1 Method of depositing dielectric 审中-公开
标题翻译：电介质沉积方法
公开(公告)号：US20010041460A1
公开(公告)日：2001-11-15
申请号：US09832942
申请日：2001-04-12
发明人： Claire Louise Wiggins
IPC分类号： H01L021/326 , H01L021/479 , H01L021/31
CPC分类号： H01L21/02266 , C23C14/0036 , C23C14/083 , C23C14/5826 , C23C14/5853 , H01G4/1254 , H01L21/02183 , H01L21/02323 , H01L21/0234 , H01L21/31604
摘要： This invention relates to a method of depositing dielectric on a semiconductor substrate to form part of a capacitor. The method includes reactive sputtering a metal oxide layer from a target of metal onto the substrate wherein the support is biased to induce a DC voltage across the depositing dielectric as it forms. The voltage may be in the range of 200-300V.
摘要翻译：本发明涉及一种在半导体衬底上沉积电介质以形成电容器的一部分的方法。该方法包括将金属氧化物层从金属靶反应溅射到衬底上，其中支撑体在其形成时被偏置以引导跨越沉积电介质的直流电压。电压可能在200-300V的范围内。

5. 发明申请

US20040217441A1 Area efficient stacking of antifuses in semiconductor device 有权
标题翻译：半导体器件中反熔丝的区域有效堆叠
公开(公告)号：US20040217441A1
公开(公告)日：2004-11-04
申请号：US09751474
申请日：2000-12-28
发明人： Gunther Lehmann , Axel Christoph Brintzinger , Gabriel Daniel
IPC分类号： H01L021/326 , H01L027/10
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.
摘要翻译：提供一种半导体器件，其由具有在其表面上的垂直堆叠关系中的至少两个反熔丝的区域有效布置的晶片形成，并且在其间共享公共中间电极。该装置包括至少一个下部反熔丝，其具有下部对电极和下部可熔绝缘体部分，该熔断绝缘体部分限定了将下部反电极与公共中间电极互连的初始高电阻状态的下部熔丝元件，以及至少一个上部反熔丝，其可以与下部反熔丝相同或不同，上部反熔丝具有上部对电极和上部可熔绝缘体部分，其限定具有初始高电阻状态的上部熔丝元件，其将上部对置电极与公共中间电极。

6. 发明申请

US20040087052A1 Fabrication method of multisensors chips for detecting analytes 失效
标题翻译：用于检测分析物的多传感器芯片的制造方法
公开(公告)号：US20040087052A1
公开(公告)日：2004-05-06
申请号：US10345771
申请日：2003-01-16
发明人： Ioannis Katakis , Monica Campas Homs
IPC分类号： H01L021/00 , H01L021/326 , H01L021/479
CPC分类号： G01N33/54393 , B01J19/0046 , B01J2219/00527 , B01J2219/00529 , B01J2219/00648 , B01J2219/00653 , B01J2219/00722 , C40B40/06
摘要： A method includes (a) putting a multielectrodic chip lithographed in a wafer that contains between 2 and 2000 individually polarisable electrodes, in contact with a solution or suspension that includes modified colloidal particles with a (bio)chemical recognition element; (b) applying to an electrode of the multielectrodic chip, a potential between null1 and null2V vs. Ag/AgCl saturated, for a period of time between 1 and 300 seconds; (c) washing the chip after this stage (b); and (d) repeat the steps (b) and (c) as many times as needed to deposit a (bio)chemical recognition element, same or different to the one or ones previously deposited, on each one of the electrodes of that chip. The method is applicable for the fabrication of multisensors, particularly in chips and arrays for analytical and diagnostic applications.
摘要翻译：一种方法包括（a）将包含2至2000个单独可极化电极的晶片中的多电极芯片放置在与包含改性胶体颗粒与（生物）化学识别元件的溶液或悬浮液接触的晶片上; （b）施加到多电极芯片的电极上，在-1和+2V之间的电势与Ag / AgCl饱和的时间在1和300秒之间; （c）在该阶段（b）之后洗涤芯片; 和（d）根据需要重复步骤（b）和（c），以沉积与该芯片的每个电极相同或不同于之前沉积的一个或多个的（生物）化学识别元件。该方法适用于制造多传感器，特别是用于分析和诊断应用的芯片和阵列。

7. 发明申请

US20030145303A1 Method for activating fuse units in electronic circuit device 失效
标题翻译：在电子电路装置中激活熔丝单元的方法
公开(公告)号：US20030145303A1
公开(公告)日：2003-07-31
申请号：US10325100
申请日：2002-12-20
申请人： Infineon Technologies AG
发明人： Gerd Frankowsky
IPC分类号： G06F017/50 , H01L021/326
CPC分类号： G11C17/18 , G11C29/785
摘要： The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the electronic circuit device (100), where an electronic circuit device (100) in which fuse units (101a-101n) can be activated is selected, those fuse units (101a-101n) in the selected electronic circuit device (100) which can be activated in order to modify the circuit design for the electronic circuit device (100) are determined, the fuse units (101a-101n) which can be activated in order to mosdify the circuit design for the electronic circuit device (100) are addressed using fuse addressing units (102a-102n), and an activation state of the fuse units (101a-101n) which can be activated in order to modify the circuit design for the electronic circuit device (100) is stipulated, the fuse units (101a-101n) addressed using the fuse addressing units (102a-102n) being activated using fuse activation units (103a-103n) in line with the stipulated activation state.
摘要翻译：本发明提供一种用于激活电子电路装置（100）中的熔丝单元（101a-101n）的方法，以便修改电子电路装置（100）的电路设计，其中电子电路装置（100）（101a-101n）被选择时，确定为了修改电子电路装置（100）的电路设计可以激活的所选电子电路装置（100）中的那些熔丝单元（101a-101n）可以使用熔丝寻址单元（102a-102n）来寻址能够激活电子电路装置（100）的电路设计的保险丝单元（101a-101n），并且保险丝单元（101a- 为了修改电子电路装置（100）的电路设计，可以激活可激活的熔丝单元（101a-101n），使用熔丝寻址单元（102a-102n）寻址的熔丝单元（101a-101n）使用熔丝激活单元 103a-103n）符合规定激活状态。

8. 发明申请

US20030036250A1 Operation method for programming and erasing a data in a P-channel sonos memory cell 有权
标题翻译：用于编程和擦除P信道声纳存储单元中的数据的操作方法
公开(公告)号：US20030036250A1
公开(公告)日：2003-02-20
申请号：US10005270
申请日：2001-12-04
发明人： Hung-Sui Lin , Nian-Kai Zous , Han-Chao Lai , Tao-Cheng Lu
IPC分类号： H01L021/326 , H01L021/479 , H01L021/31
CPC分类号： G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.
摘要翻译：一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。两个掺杂区域被设置为漏极区域和源极区域。当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。第三负电压大于绝对值中的第二负偏压。

9. 发明申请

US20020166570A1 Cleaning method for semiconductor manufacturing process to prevent metal corrosion 有权
标题翻译：半导体制造工艺的清洗方法，防止金属腐蚀
公开(公告)号：US20020166570A1
公开(公告)日：2002-11-14
申请号：US09871534
申请日：2001-05-31
发明人： Chung-Tai Chen
IPC分类号： B08B003/08 , H01L021/302 , H01L021/461 , H01L021/311 , H01L021/326 , H01L021/479
CPC分类号： H01L21/02071 , B08B3/10
摘要： A cleaning method for semiconductor manufacturing process. A to-be-cleaned wafer having a metal layer thereon is provided. The wafer is placed into a chemical cleaning equipment unit to clean the wafer surface with a chemical cleaning solution while protecting the metal layer by a cathodic protection method. Next, the chemical cleaning solution on the wafer surface is rinsed away and the wafer is then dried to complete the cleaning method.
摘要翻译：一种半导体制造工艺的清洗方法。提供其上具有金属层的待清洁晶片。将晶片放置在化学清洁设备单元中以用化学清洁溶液清洁晶片表面，同时通过阴极保护方法保护金属层。接下来，将晶片表面上的化学清洁溶液冲洗掉，然后干燥晶片以完成清洁方法。

10. 发明申请

US20020001865A1 ANTIFUSE STRUCTURES WITH IMPROVED MANUFACTURABILITY 失效
标题翻译：具有改进的可制造性的抗结构
公开(公告)号：US20020001865A1
公开(公告)日：2002-01-03
申请号：US09183948
申请日：1998-10-31
发明人： GUOBIAO ZHANG
IPC分类号： H01L021/326
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S438/907 , Y10S438/908 , H01L2924/00
摘要： An antifuse structure of the present invention comprises an antifuse layer and a bottom electrode which are immune to the damages caused by harmful processing environment. The three major components of the antifusenullthe bottom electrode, the antifuse layer and the top buffer layernullare formed consecutively without any photolithography or etching step in-between. The top buffer layer is defined before the bottom electrode. This antifuse structure can substantially improve the antifuse manufacturability.
摘要翻译：本发明的反熔丝结构包括反熔丝层和底部电极，其免受由有害处理环境造成的损害。反熔丝的三个主要部件 - 底部电极，反熔丝层和顶部缓冲层 - 不间断地形成任何光刻或蚀刻步骤。顶部缓冲层定义在底部电极之前。这种反熔丝结构可以显着提高反熔丝的可制造性。

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