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1. 发明专利

AU2001281594B2 Fabrication of nanoelectronic circuits 未知
公开(公告)号：AU2001281594B2
公开(公告)日：2005-08-25
申请号：AU2001281594
申请日：2001-08-24
申请人： UNISEARCH LTD
发明人： CLARK ROBERT GRAHAM , BUEHLER TILO MARKUS , BRENNER ROLF , MCKINNON RITA PATRICIA , LUMPKIN NANCY ELLEN , HAMILTON ALEXANDER RUDOLF , DZURAK ANDREW STEVEN
IPC分类号： G03F7/26 , G03F7/20 , G06N99/00 , H01L21/027 , H01L21/266 , H01L21/335 , H01L21/336 , H01L29/66 , H01L29/78 , H01L49/00 , G03F007/20 , G01N001/00 , H01L021/3105 , H01L021/266
摘要： A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

2. 发明专利

AU2001281594B9 Fabrication of nanoelectronic circuits 未知
公开(公告)号：AU2001281594B9
公开(公告)日：2005-09-01
申请号：AU2001281594
申请日：2001-08-24
申请人： NEWSOUTH INNOVATIONS PTY LTD
发明人： CLARK ROBERT GRAHAM , BUEHLER TILO MARKUS , BRENNER ROLF , MCKINNON RITA PATRICIA , LUMPKIN NANCY ELLEN , HAMILTON ALEXANDER RUDOLF , DZURAK ANDREW STEVEN
IPC分类号： G03F7/26 , G03F7/20 , G06N99/00 , H01L21/027 , H01L21/266 , H01L21/335 , H01L21/336 , H01L29/66 , H01L29/78 , H01L49/00 , G03F007/20 , G01N001/00 , H01L021/3105 , H01L021/266
摘要： A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

3. 发明申请

US20010000409A1 Method for ashing and apparatus employable for ashing 失效
标题翻译：灰化方法和可用于灰化的设备
公开(公告)号：US20010000409A1
公开(公告)日：2001-04-26
申请号：US09738308
申请日：2000-12-18
发明人： Toshiro Mitsuhashi
IPC分类号： H01L021/3105 , H01L021/31 , H01L021/469 , H01L021/47 , H01L021/475 , H01L021/4757
CPC分类号： H01L21/31138 , Y10S134/902
摘要： A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 120null C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150null C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.
摘要翻译：一种用于灰化由先前进行的离子注入工艺引起的由硬化层覆盖的抗蚀剂图案的方法，包括用于在第一温度下进行灰化处理的第一步骤，例如， 120℃或更少，其中不发生爆裂现象，用于去除硬化层;以及第二步骤，用于在第二温度下进行灰化过程，例如，为了完全除去剩余的抗蚀剂图案，可以使灰度为高的150℃，以及用于灰化由硬化层覆盖的抗蚀剂图案的方法的设备，该硬化层包括用于上下移动半导体晶片的机构，以调节并且包括介于半导体晶片和加热器之间的快门。

4. 发明申请

US20010006166A1 REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE 有权
标题翻译：在A1 / CU金属线上去除后置聚合物
公开(公告)号：US20010006166A1
公开(公告)日：2001-07-05
申请号：US09204706
申请日：1998-12-03
发明人： RAVIKUMAR RAMACHANDRAN , WESLEY NATZLE , MARTIN GUTSCHE , HIROYUKI AKATSU , CHIEN YU
IPC分类号： H01L021/461 , H01L021/302 , C23F003/00 , C03C025/68 , H01L021/28 , H01L021/3105 , C23F017/00
CPC分类号： H01L21/02071 , H01L21/02054 , H01L21/31138 , H01L21/32136 , Y10S134/902
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water soluble material with deionized water.
摘要翻译：一种用于去除半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水等离子体工艺以剥离先前经过RIE工艺的半导体或微电子复合结构的光致抗蚀剂层; 将一种蚀刻气体和酸中和气体的混合物供给到所述结构被支撑的真空室中，以形成从RIE工艺在Al / Cu金属管线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水除去水溶性物质。

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