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    • 5. 发明授权
    • Method for heteroepitaxial growth using multiple MBE chambers
    • 使用多个MBE室的异质外延生长方法
    • US4786616A
    • 1988-11-22
    • US61069
    • 1987-06-12
    • Muhammad A. AwalEl Hang Lee
    • Muhammad A. AwalEl Hang Lee
    • C30B23/02H01L21/306H01L21/205
    • C30B23/02Y10S148/021Y10S148/169
    • A method for epitaxially growing a layer of III-V material on a wafer of a material such as silicon comprises the steps of placing the wafer (16') in a first ultra-high vacuum chamber (11), and epitaxially growing a transition layer such as germanium on the wafer. An intermediate high vacuum chamber (13) is used to transport the wafer 16' to a second ultra-high vacuum chamber (12), and the second chamber (12) is used to epitaxially grow a layer of III-V material over the transition layer. Gate valves (33 and 15) are sequentially opened and closed to that the second vacuum chamber (12) cannot be contaminated by gases or particles from the first vacuum chamber (11). Wafer transport from chamber (11) to (13) is achieved without exposure to the atmosphere or to significant pressure changes thus avoiding the waste of transfer time or the formation of native oxide on the wafer surface.
    • 在诸如硅的材料的晶片上外延生长III-V材料层的方法包括以下步骤:将晶片(16')放置在第一超高真空室(11)中,并且外延生长过渡层 例如晶圆上的锗。 使用中间高真空室(13)将晶片16'输送到第二超高真空室(12),并且第二室(12)用于在过渡段外延生长III-V材料层 层。 闸阀(33和15)依次打开和关闭,使得第二真空室(12)不会被来自第一真空室(11)的气体或颗粒污染。 从室(11)到(13)的晶片传输是在没有暴露于大气的情况下实现的,或者显着的压力变化,从而避免了在晶片表面上浪费转移时间或自然氧化物的形成。
    • 8. 发明授权
    • Method for fabrication of monolithic integrated circuits
    • 单片集成电路制造方法
    • US4789645A
    • 1988-12-06
    • US40418
    • 1987-04-20
    • Joseph A. CalvielloPaul R. BieRonald J. Pomian
    • Joseph A. CalvielloPaul R. BieRonald J. Pomian
    • H01L21/70H01L21/8252H01L29/48H01L21/283
    • H01L21/707H01L21/8252Y10S148/014Y10S148/021Y10S438/913
    • During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps. An all-refractory MESFET is described, having a Schottky barrier gate and nonalloyed ohmic contacts for source and drain producible at room temperatures. Source, gate, and drain can be defined with a single mask. A thinner gold layer is formed for FET contacts than for other circuit conductors and elements by means of a configured tantalum layer buried in a thick gold layer.
    • 在制造单片微波集成电路期间,首先提供具有源极,栅极,漏极和/或肖特基势垒结的有源器件用于外延层。 然后在原地生产许多层金属和氧化物,而不从其环境室中移除电路。 然后通过光刻和从芯片的顶部向下的其它处理顺序地处理许多层来定义电路元件。 选择金属,氧化物和工艺的某些组合以使得能够以这种方式从上到下制造电路。 这减少了污染化学膜和颗粒在所需层之间的包含。 集中和分布式电容器,电阻器,电感器,传输线,触点和完整的有源器件都是单片定义的,数量减少的工艺步骤。 描述了全难熔MESFET,其具有肖特基势垒栅极和用于在室温下可产生的源极和漏极的非合金欧姆接触。 源,栅极和漏极可以用单个掩模定义。 通过埋在厚金层中的配置的钽层,为FET触点形成更薄的金层,而不是其他电路导体和元件。