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1. 发明授权

US08035436B2 Passive capacitively injected phase interpolator 有权
标题翻译：被动电容注入相位内插器
公开(公告)号：US08035436B2
公开(公告)日：2011-10-11
申请号：US12566506
申请日：2009-09-24
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03H11/16
CPC分类号： H03D13/00
摘要： A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal.
摘要翻译：描述了相位插值器电路。在相位插值器电路中，基于第一参考信号和第二参考信号的加权求和产生具有基频和相位的输出信号，其中第一参考信号具有基频和第一相位，第二参考信号具有相同的基频和第二相位。注意，基于相位插值器电路中的加权电路中的相关联的第一和第二阻抗值来确定第一参考信号和第二参考信号对输出信号的贡献。例如，可以使用两个电容器的可编程电容比来在第一参考信号和第二参考信号之间进行内插。另外，相位插值器电路可以包括向加权电路提供DC偏置并且放大加权电路的输出以提供输出信号的偏置电路。

2. 发明申请

US20110068827A1 PASSIVE CAPACITIVELY INJECTED PHASE INTERPOLATOR 有权
标题翻译：被动电容式注入式相位插补器
公开(公告)号：US20110068827A1
公开(公告)日：2011-03-24
申请号：US12566506
申请日：2009-09-24
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03D13/00
CPC分类号： H03D13/00
摘要： A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal.
摘要翻译：描述了相位插值器电路。在相位插值器电路中，基于第一参考信号和第二参考信号的加权求和产生具有基频和相位的输出信号，其中第一参考信号具有基频和第一相位，第二参考信号具有相同的基频和第二相位。注意，基于相位插值器电路中的加权电路中的相关联的第一和第二阻抗值来确定第一参考信号和第二参考信号对输出信号的贡献。例如，可以使用两个电容器的可编程电容比来在第一参考信号和第二参考信号之间进行内插。另外，相位插值器电路可以包括向加权电路提供DC偏置并且放大加权电路的输出以提供输出信号的偏置电路。

3. 发明授权

US07994832B2 Aperture generating circuit for a multiplying delay-locked loop 有权
标题翻译：用于倍增延迟锁定环路的光圈产生电路
公开(公告)号：US07994832B2
公开(公告)日：2011-08-09
申请号：US12613936
申请日：2009-11-06
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03L7/00
CPC分类号： H03L7/16 , H03L7/0816
摘要： A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.
摘要翻译：描述了乘法延迟锁定环路（MDLL）。在MDLL中，相位插值器（PI）通过将两个内部信号（其具有不同相位）与来自MDLL中的延迟元件的序列相混合来向选择控制逻辑提供校正信号。该校正信号补偿与选择控制逻辑相关联的延迟，从而确保由选择控制逻辑输出到选择电路（例如多路复用器）的选择脉冲或信号被适当地定时，使得选择电路可以选择性地注入锁定在参考信号中使用边缘的延迟元件的序列。

4. 发明授权

US08116420B2 Clock-forwarding technique for high-speed links 有权
标题翻译：用于高速链路的时钟转发技术
公开(公告)号：US08116420B2
公开(公告)日：2012-02-14
申请号：US12642348
申请日：2009-12-18
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03D3/24
CPC分类号： H04L25/247 , H03L7/0805 , H04L7/0012
摘要： A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.
摘要翻译：描述了诸如时钟再生和乘法电路的中继器电路。在该中继器电路中，时钟倍增器单元（CMU）基于在链路上接收到的转发时钟信号产生内部时钟信号。此外，中继器电路中的相位插值器（PI）基于转发的时钟信号和内部时钟信号来提供输出时钟信号。注意，CMU和PI滤波器减少转发的时钟信号和内部时钟信号中的周期到周期抖动，并且输出时钟信号具有作为转发的时钟信号的相位的加权平均的相位，以及内部时钟信号。此外，可以基于链路上的位置或位置来调整所转发的时钟信号和内部时钟信号的相对权重（即，相位平均和抖动滤波的量）。

5. 发明申请

US20110150159A1 CLOCK-FORWARDING TECHNIQUE FOR HIGH-SPEED LINKS 有权
标题翻译：用于高速链接的时钟转发技术
公开(公告)号：US20110150159A1
公开(公告)日：2011-06-23
申请号：US12642348
申请日：2009-12-18
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H04L7/00
CPC分类号： H04L25/247 , H03L7/0805 , H04L7/0012
摘要： A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.
摘要翻译：描述了诸如时钟再生和乘法电路的中继器电路。在该中继器电路中，时钟倍增器单元（CMU）基于在链路上接收到的转发时钟信号产生内部时钟信号。此外，中继器电路中的相位插值器（PI）基于转发的时钟信号和内部时钟信号来提供输出时钟信号。注意，CMU和PI滤波器减少转发的时钟信号和内部时钟信号中的周期到周期抖动，并且输出时钟信号具有作为转发的时钟信号的相位的加权平均的相位，以及内部时钟信号。此外，可以基于链路上的位置或位置来调整所转发的时钟信号和内部时钟信号的相对权重（即，相位平均和抖动滤波的量）。

6. 发明申请

US20110109356A1 APERTURE GENERATING CIRCUIT FOR A MULTIPLYING DELAY-LOCKED LOOP 有权
标题翻译：用于多路延迟锁定环路的光电发生电路
公开(公告)号：US20110109356A1
公开(公告)日：2011-05-12
申请号：US12613936
申请日：2009-11-06
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03L7/0816
摘要： A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.
摘要翻译：描述了乘法延迟锁定环路（MDLL）。在MDLL中，相位插值器（PI）通过将两个内部信号（其具有不同相位）与来自MDLL中的延迟元件的序列相混合来向选择控制逻辑提供校正信号。该校正信号补偿与选择控制逻辑相关联的延迟，从而确保由选择控制逻辑输出到选择电路（例如多路复用器）的选择脉冲或信号被适当地定时，使得选择电路可以选择性地注入锁定在参考信号中使用边缘的延迟元件的序列。

7. 发明授权

US07030470B1 Using chip lamination to couple an integrated circuit with a microstrip transmission line 有权
标题翻译：使用芯片层压将集成电路与微带传输线耦合
公开(公告)号：US07030470B1
公开(公告)日：2006-04-18
申请号：US10844196
申请日：2004-05-11
申请人： Ronald Ho , Robert J. Drost , Chih-Kong Ken Yang
发明人： Ronald Ho , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H01L39/00
CPC分类号： H01L23/66 , H01L23/481 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/82 , H01L24/83 , H01L2223/6627 , H01L2224/2402 , H01L2224/48091 , H01L2224/4813 , H01L2224/49175 , H01L2224/4943 , H01L2224/81193 , H01L2224/81801 , H01L2224/83894 , H01L2924/00014 , H01L2924/14 , H01L2924/1903 , H01L2924/30107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.
摘要翻译：本发明的一个实施例提供了一种通过芯片层压将集成电路与微带传输线可操作地耦合的系统。该系统包括包含集成电路的第一半导体管芯和包含微带传输线的第二半导体管芯。与集成电路中具有相对小的横截面的金属线不同，微带传输线具有足够大的横截面，使得信号传播由电感和电容（LC）代替电阻和电容（RC）来控制，。将第一半导体管芯和第二半导体管芯层叠在一起，使得第一半导体管芯上的集成电路与第二半导体管芯中的微带传输线可操作地耦合。

8. 发明授权

US09306849B2 Methods and systems for managing distribute media access control address tables 有权
标题翻译：用于管理分发媒体访问控制地址表的方法和系统
公开(公告)号：US09306849B2
公开(公告)日：2016-04-05
申请号：US13842867
申请日：2013-03-15
申请人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
发明人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
IPC分类号： H04L12/743 , H04L12/721
CPC分类号： H04L49/25 , H04L45/66 , H04L45/7457 , H04L69/22
摘要： Methods, systems, and computer programs are presented for switching a network packet. One method includes operations for receiving a packet having a media access control (MAC) address, and for switching the packet by a first packet switching device (PSD) when the MAC address is present in a first memory. Further, the method includes operations for transferring the packet to a second PSD when the MAC address is absent from the first memory and present in a second memory associated with the second PSD, and for transferring the packet to a third PSD when the MAC address is absent from the first memory and the second memory.
摘要翻译：呈现用于切换网络分组的方法，系统和计算机程序。一种方法包括用于接收具有媒体访问控制（MAC）地址的分组的操作，以及当MAC地址存在于第一存储器中时由第一分组交换设备（PSD）切换分组的操作。此外，该方法包括当MAC地址不存在于第一存储器中且存在于与第二PSD相关联的第二存储器中时将数据包传送到第二PSD的操作，并且当MAC地址为缺少第一个内存和第二个内存。

9. 发明申请

US20130235870A1 Methods, Systems, and Fabrics Implementing a Distributed Network Operating System 有权
标题翻译：方法，系统和结构实现分布式网络操作系统
公开(公告)号：US20130235870A1
公开(公告)日：2013-09-12
申请号：US13842806
申请日：2013-03-15
申请人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
发明人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
IPC分类号： H04L12/56
CPC分类号： H04L41/5019 , H04L45/56 , H04L45/66 , H04L47/803 , H04L49/65 , H04L49/70
摘要： Methods, systems, and computer programs are presented for managing a switching layer fabric. A network device operating system (ndOS) program includes program instructions for exchanging switching policy regarding a switching of network packets in a plurality of ndOS switching devices having respective ndOS programs executing therein. The first ndOS program is executed in a first ndOS switching device, and the switching policy is exchanged with other ndOS programs via multicast messages. Further, the ndOS program includes program instructions for exchanging resource control messages with the other ndOS switching devices to implement service level agreements in the switching layer fabric, where the ndOS switching devices cooperate to enforce the service level agreements. Further yet, the ndOS program includes program instructions for receiving changes to the switching policy, and program instructions for propagating the received changes to the switching policy via message exchange between the ndOS programs. The ndOS switching devices are managed as a single logical switch that spans the plurality of ndOS switching devices.
摘要翻译：提出了用于管理交换层结构的方法，系统和计算机程序。网络设备操作系统（ndOS）程序包括用于交换交换策略的程序指令，所述交换策略涉及在其中执行各自的ndOS程序的多个ndOS交换设备中的网络分组的切换。第一ndOS程序在第一ndOS交换设备中执行，并且交换策略通过多播消息与其他ndOS程序交换。此外，ndOS程序包括用于与其他ndOS交换设备交换资源控制消息的程序指令，以实现交换层架构中的服务级别协议，其中ndOS交换设备协作以执行服务级别协议。此外，ndOS程序包括用于接收对切换策略的改变的程序指令，以及用于通过ndOS程序之间的消息交换将接收的改变传播到切换策略的程序指令。 ndOS交换设备被管理为跨越多个ndOS交换设备的单个逻辑交换机。

10. 发明授权

US08891543B1 Method and system for processing packets in a network device 有权
标题翻译：在网络设备中处理数据包的方法和系统
公开(公告)号：US08891543B1
公开(公告)日：2014-11-18
申请号：US13478179
申请日：2012-05-23
申请人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
发明人： Sunay Tripathi , Robert James Drost , Chih-Kong Ken Yang
IPC分类号： H04L12/56
CPC分类号： H04L47/35 , H04L12/4641 , H04L45/66 , H04L47/196
摘要： In general, the invention relates to a network device that includes a port configured to receive a packet and a packet processor (PP) configured to receive the packet from the port, in response to receiving the packet, make a first determination that a trigger condition exists, and in response to the first determination, issue a configuration action, where the configuration action, when performed by the network device, modifies a configuration of a component on the network device.
摘要翻译：通常，本发明涉及一种网络设备，其包括被配置为接收分组的端口和被配置为响应于接收到分组而从该端口接收分组的分组处理器（PP），首先确定触发条件存在，并且响应于第一确定，发出配置动作，其中配置动作在由网络设备执行时修改网络设备上的组件的配置。

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