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1. 发明申请

WO2003098231A3 MONOLITHIC I-LOAD ARCHITECTURES FOR AUTOMATIC TEST EQUIPMENT 审中-公开
公开(公告)号：WO2003098231A3
公开(公告)日：2003-11-27
申请号：PCT/US2003/014456
申请日：2003-05-09
申请人： TELASIC COMMUNICATIONS, INC.
发明人： LINDER, Lloyd, F.
IPC分类号： H03K5/08
摘要： An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source (IL), a current sink (IH), a current switching circuit (D1-D4) and a control circuit (Q23-Q26) for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as a voltage difference between a fixed reference voltage and a pin output of a device under test.

2. 发明申请

WO2003098822A1 RF TRANSCEIVER WITH LOW POWER CHIRP ACQUISTION MODE 审中-公开
标题翻译：射频收发器，具有低功率CHIRP采集模式
公开(公告)号：WO2003098822A1
公开(公告)日：2003-11-27
申请号：PCT/US2003/014444
申请日：2003-05-09
申请人： TelASIC COMMUNICATIONS, INC.
发明人： LINDER, Lloyd, F. , FELDER, Benjamin , DEVENDORF, Don, C.
IPC分类号： H04B1/38
CPC分类号： H04B1/69 , H04B2001/6912
摘要： An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit (12), which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast hopping LO generator (32) is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter (24) connected to filter the demodulated output (22) is arranged to extend the width of its passband to include the chirp rate. The filtered signal (26) is digitized with an ADC (28) and processed to determine the incoming signal's chirp rate. Once the chirp rate is detected, the LO power generator (32) is powered down, the passband of the active bandpass filter (24) is narrowed, and the remaining receiver circuitry is powered up to dechirp the RF input signal.
摘要翻译：具有低功率啁啾获取模式的RF收发器包括脉冲检测电路（12），其在接收到适当的输入脉冲时启动低功率啁啾获取模式。在线性调频采集模式下，无需确定啁啾率的所有收发器电路都被掉电，低功率快速LO发生器（32）被加电以提供一个或多个LO信号来解调输入信号，并且有源带通滤波器（24）被连接以对解调的输出（22）进行滤波，被布置成扩展其通带的宽度以包括啁啾率。滤波后的信号（26）用ADC（28）数字化，并被处理以确定输入信号的啁啾率。一旦检测到啁啾速率，LO功率发生器（32）断电，有源带通滤波器（24）的通带变窄，剩余的接收机电路通电以使RF输入信号去除。

3. 发明申请

WO2003098231A2 MONOLITHIC I-LOAD ARCHITECTURES FOR AUTOMATIC TEST EQUIPMENT 审中-公开
标题翻译：用于自动测试设备的单片I-LOAD架构
公开(公告)号：WO2003098231A2
公开(公告)日：2003-11-27
申请号：PCT/US2003/014456
申请日：2003-05-09
申请人： TELASIC COMMUNICATIONS, INC.
发明人： LINDER, Lloyd, F.
IPC分类号： G01R
CPC分类号： G01R31/2834
摘要： An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the current source and the current sink; and to a control circuit for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as a voltage difference between a fixed reference voltage and a pin output voltage of a device under test.
摘要翻译：用于测试集成电路的自动测试设备的有源负载电路。有源负载电路包括电流源; 电流槽电流开关电路具有分别连接到电流源和电流吸收器的电流源和电流汇点; 以及控制电路，用于以与被测器件的固定参考电压和引脚输出电压之间的电压差在振幅和极性相同的差分电压来控制电流开关电路。

4. 发明申请

WO2002037685A3 HIGH RESOLUTION ADC BASED ON AN OVERSAMPLED SUBRANGING ADC 审中-公开
公开(公告)号：WO2002037685A3
公开(公告)日：2002-05-10
申请号：PCT/US2001/032617
申请日：2001-10-15
申请人： TELASIC COMMUNICATIONS, INC.
发明人： DEVENDORF, Don, C. , FELDER, Benjamin , LINDER, Lloyd, F.
IPC分类号： H03M1/14
摘要： A high performance ADC apparatus. The invention apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baselien data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution. The method for producing this result includes providing the baseline device having a selected dynamic range at a baseline clock rate; generating the baseline clock rate by translating a reference clock upward by a selected factor; decimating the data rate of the baseline device to a slower data rate so as to achieve a selected degree of oversampling; and producing an output data rate as a sub-multiple of the baseline clock rate with the selected output resolution at the slower data rate. The architecture includes a monolithic substrate on which the baseline ADC provides a dynamic range necessary to satisfy the performance requirements of the final ADC.

5. 发明授权

EP0908003B1 TEMPERATURE COMPENSATED AMPLIFIER 失效
标题翻译：温度补偿放大器
公开(公告)号：EP0908003B1
公开(公告)日：2004-03-17
申请号：EP98918064.1
申请日：1998-04-09
申请人： TelASIC Communications, Inc.
发明人： HIEU, M., Le , LINDER, Lloyd, F. , HIRATA, Erick, M. , DEVENDORF, Don, C.
IPC分类号： H03F1/30
CPC分类号： H03F1/302

6. 发明授权

EP1057263B1 HIGH SPEED PIN DRIVER INTEGRATED CIRCUIT ARCHITECTURE FOR COMMERCIAL AUTOMATIC TEST EQUIPMENT APPLICATIONS 有权
标题翻译：集成的电路架构用于快速引脚驱动器为市售的自动测试设备应用
公开(公告)号：EP1057263B1
公开(公告)日：2003-05-21
申请号：EP99967393.2
申请日：1999-12-16
申请人： TelASIC Communications, Inc.
发明人： LINDER, Lloyd, F.
IPC分类号： H03K19/003 , H03K17/66 , G01R31/319 , H03K19/018
CPC分类号： H03K19/01837 , G01R31/31924 , H03K19/00376 , H03K19/01806
摘要： An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out. The replica biasing is implemented using a current mirror circuit, a summing device and a buffer circuit which generates the voltage replica in an active mode of the PIN driver circuit. The replica biasing scheme used in the present invention tracks over temperature and process, and provides for improved high speed circuitry without the need for calibration of leakage currents in the inhibit mode.

7. 发明授权

EP0906662B1 LOW VOLTAGE ANALOG FRONT END 失效
标题翻译：模拟输入电路的低电压
公开(公告)号：EP0906662B1
公开(公告)日：2003-03-26
申请号：EP98915531.2
申请日：1998-04-09
申请人： TelASIC Communications, Inc.
发明人： CHEN, Ricky, Y. , LINDER, Lloyd, F. , DEVENDORF, Don, C.
IPC分类号： H03F3/45 , H03F3/343
CPC分类号： H03F3/45071 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0033 , H03D2200/0043 , H03F3/343

8. 发明公开

EP1285494A2 LOW NOISE, LOW DISTORTION, GILBERT CELL MIXER WITH GAIN CONTROL , AND METHOD 审中-公开
标题翻译：增益控制，和方法，低噪音低失真吉尔伯特单元混频器
公开(公告)号：EP1285494A2
公开(公告)日：2003-02-26
申请号：EP01937763.9
申请日：2001-05-24
申请人： TelASIC Communications, Inc.
发明人： LINDER, Lloyd, F. , DUONG, Clifford, N. , DEVENDORF, Don, C.
IPC分类号： H03D7/00
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1458 , H03D7/1491
摘要： The specific embodiment, includes a mixing circuit (100). The mixing circuit (100) includes Gilbert cells (102, 104, 108 and 109) and circuitry for providing automatic gain control (90) for each of the channels. The Gilbert cells (102, 104, 108 and 109) and the automatic gain control circuitry are driven by a transconductance amplifier (120) and therefore operate in a current mode. Differential digital automatic gain control signals are provided in response to a channel select signal from a digital control circuit. The circuit provides multiple IF channels which may be filtered individually.

9. 发明授权

EP0910895B1 CURRENT FEEDBACK DIFFERENTIAL AMPLIFIER CLAMP 失效
标题翻译：端子电路用于差分放大器，电流反馈
公开(公告)号：EP0910895B1
公开(公告)日：2003-03-26
申请号：EP98918059.1
申请日：1998-04-09
申请人： TelASIC Communications, Inc.
发明人： HIEU, M., Le , HIRATA, Erick, M. , KOSAKA, Roger, N. , LINDER, Lloyd, F. , FELDER, Benjamin , McMULLIN, Donald, G. , TRAN, Kelvin, T.
IPC分类号： H03F1/52 , H03F3/30
CPC分类号： H03F3/3076 , H03F1/52
摘要： A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.

10. 发明授权

EP0909479B1 DIFFERENTIAL PAIR GAIN CONTROL STAGE 失效
标题翻译：增益控制水平FOR差分放大器
公开(公告)号：EP0909479B1
公开(公告)日：2004-04-21
申请号：EP98920924.2
申请日：1998-04-30
申请人： TelASIC Communications, Inc.
发明人： CHEN, Ricky, Y. , LINDER, Lloyd, F. , DEVENDORF, Don, C. , GORDER, Matthew, S.
IPC分类号： H03G1/00
CPC分类号： H03G1/0023 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0047
摘要： A 'gain control differential pair' (GCDP) (10) conducts current in response to a differential drive signal, with the gain of a signal path formed via the current circuit of one of its transistors controlled by the drive signal. The GCDP is preferably driven with a drive circuit (20) that receives a symmetrical input signal and produces an offset differential drive signal which has the effect of keeping one of the GCDP's transistors turned off over a wider portion of a symmetrical input signal's voltage range, thereby reducing GCDP-caused noise. One or more GCDPs are implemented as part of a Gilbert mixer (30) to regulate the amount of RF current that flows between the mixer's output and input stages, which eliminates the need to provide gain control in other circuits fed by the mixer. When driven with an offset drive signal, the Gilbert mixer simultaneously provides gain control, low distortion, low power consumption and excellent LO/RF isolation.

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