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1. 发明公开

CN106549001A 具有再分布焊盘的半导体装置有权
公开(公告)号：CN106549001A
公开(公告)日：2017-03-29
申请号：CN201610675009.1
申请日：2016-08-16
申请人：三星电子株式会社
发明人：朴明洵 , 郑显秀 , 金原永 , 张爱妮 , 李灿浩
IPC分类号： H01L23/498
CPC分类号： H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要：公开了具有再分布焊盘的半导体装置。所述半导体装置包括设置在半导体基板上的多个电焊盘以及电连接到电焊盘和外部端子的多个再分布焊盘。所述多个再分布焊盘包括构成用于第一电信号的传输路径的多个第一再分布焊盘以及构成用于与第一电信号不同的第二电信号的传输路径的至少一个第二再分布焊盘。第一再分布焊盘布置在半导体基板上以形成至少两行，所述至少一个第二再分布焊盘设置在所述至少两行第一再分布焊盘之间。

2. 发明申请

US20170373035A1 FAN-OUT SEMICONDUCTOR PACKAGE MODULE 有权
公开(公告)号：US20170373035A1
公开(公告)日：2017-12-28
申请号：US15478374
申请日：2017-04-04
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Yong Jin SEOL , Yong Koon LEE
IPC分类号： H01L23/00 , H01L25/18
CPC分类号： H01L24/25 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/24 , H01L25/105 , H01L25/18 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06177 , H01L2224/06182 , H01L2224/13024 , H01L2224/14131 , H01L2224/14135 , H01L2224/14181 , H01L2224/16227 , H01L2224/24105 , H01L2224/24226 , H01L2224/25171 , H01L2224/2518 , H01L2924/19102
摘要： A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

3. 发明申请

US20170084559A1 SEMICONDUCTOR DEVICES WITH REDISTRIBUTION PADS 有权
公开(公告)号：US20170084559A1
公开(公告)日：2017-03-23
申请号：US15230889
申请日：2016-08-08
申请人： Samsung Electronics Co., Ltd.
发明人： Myeong Soon Park , Hyunsoo Chung , Won-young Kim , Ae-nee Jang , Chanho Lee
IPC分类号： H01L23/00
CPC分类号： H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要： Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

4. 发明申请

US20160233183A1 INTEGRATED CIRCUIT DIE WITH CORNER IO PADS 有权
标题翻译：集成电路与CORNER IO PADS
公开(公告)号：US20160233183A1
公开(公告)日：2016-08-11
申请号：US14620155
申请日：2015-02-11
申请人： Shailesh Kumar , Vikas Garg , Meng Kong Lye
发明人： Shailesh Kumar , Vikas Garg , Meng Kong Lye
IPC分类号： H01L23/00
CPC分类号： H01L24/06 , H01L23/3171 , H01L24/02 , H01L24/05 , H01L2224/0235 , H01L2224/02375 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06139 , H01L2224/06179 , H01L2924/00012
摘要： An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.
摘要翻译：集成电路（IC）管芯具有位于管芯内部的每一侧的侧面输入/输出（IO）焊盘。每个模具角都有一个角落的IO垫。靠近角IO垫的侧IO垫具有限定TML访问区域的顶层金属层（TML）中的钝化区域缩短。 TML轨迹通过TML访问区域将角IO垫连接到模具内部。提供拐角IO垫使IC芯片能够具有比不具有任何拐角IO垫的可比较的常规IC芯片多达四个IO垫，或IC芯片在更小的总体占地面积内具有相同数量的IO焊盘。

5. 发明申请

US20150262964A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体芯片和半导体封装
公开(公告)号：US20150262964A1
公开(公告)日：2015-09-17
申请号：US14634571
申请日：2015-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Shohei Fukuda
IPC分类号： H01L23/00 , H01L23/528 , H01L23/48
CPC分类号： H01L24/49 , G06F17/5068 , H01L23/481 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/05554 , H01L2224/06133 , H01L2224/06135 , H01L2224/06139 , H01L2224/48011 , H01L2224/48091 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/386 , H03K19/018514 , H03K19/17744 , H01L2224/45099 , H01L2224/05599
摘要： The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit.
摘要翻译：驱动器半导体封装包括基底。半导体封装包括安装在基底基板上的半导体芯片。半导体芯片包括设置在半导体芯片的中心部分的芯区域，内部电路设置在芯区域中。半导体芯片包括沿着半导体芯片的一侧设置在一行中的多个IO单元区域，在多个IO单元区域的每一个中设置差分电路。半导体芯片包括设置在每个IO单元区域之上并且电连接到差分电路的非反相端子的非反相焊盘电极。半导体芯片包括设置在每个IO单元区域上方并连接到差分电路的反相端的反相焊盘电极。

6. 发明授权

US09991219B2 Fan-out semiconductor package module 有权
公开(公告)号：US09991219B2
公开(公告)日：2018-06-05
申请号：US15478374
申请日：2017-04-04
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Yong Jin Seol , Yong Koon Lee
IPC分类号： H01L23/48 , H01L23/00 , H01L25/18
CPC分类号： H01L24/25 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/24 , H01L25/105 , H01L25/18 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06177 , H01L2224/06182 , H01L2224/13024 , H01L2224/14131 , H01L2224/14135 , H01L2224/14181 , H01L2224/16227 , H01L2224/24105 , H01L2224/24226 , H01L2224/25171 , H01L2224/2518 , H01L2924/19102
摘要： A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

7. 发明授权

US09633959B2 Integrated circuit die with corner IO pads 有权
公开(公告)号：US09633959B2
公开(公告)日：2017-04-25
申请号：US14620155
申请日：2015-02-11
申请人： Shailesh Kumar , Vikas Garg , Meng Kong Lye
发明人： Shailesh Kumar , Vikas Garg , Meng Kong Lye
IPC分类号： H01L23/48 , H01L23/52 , H01L23/00 , H01L23/31
CPC分类号： H01L24/06 , H01L23/3171 , H01L24/02 , H01L24/05 , H01L2224/0235 , H01L2224/02375 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06139 , H01L2224/06179 , H01L2924/00012
摘要： An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.

8. 发明授权

US09418960B2 Semiconductor chip and semiconductor package 有权
标题翻译：半导体芯片和半导体封装
公开(公告)号：US09418960B2
公开(公告)日：2016-08-16
申请号：US14634571
申请日：2015-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Shohei Fukuda
IPC分类号： H01L29/40 , H01L23/00 , H01L23/48 , H01L23/528 , H03K19/177 , G06F17/50 , H03K19/0185
CPC分类号： H01L24/49 , G06F17/5068 , H01L23/481 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/05554 , H01L2224/06133 , H01L2224/06135 , H01L2224/06139 , H01L2224/48011 , H01L2224/48091 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/386 , H03K19/018514 , H03K19/17744 , H01L2224/45099 , H01L2224/05599
摘要： The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip includes a plurality of IO cell regions disposed in a line along a side of the semiconductor chip, a differential circuit being provided in each of the plurality of IO cell regions. The semiconductor chip includes a non-inverting pad electrode disposed above each of the IO cell regions and electrically connected to a non-inverting terminal of the differential circuit. The semiconductor chip includes an inverting pad electrode disposed above each of the IO cell regions and connected to an inverting terminal of the differential circuit.
摘要翻译：驱动器半导体封装包括基底。半导体封装包括安装在基底基板上的半导体芯片。半导体芯片包括设置在半导体芯片的中心部分的芯区域，内部电路设置在芯区域中。半导体芯片包括沿着半导体芯片的一侧设置在一行中的多个IO单元区域，在多个IO单元区域的每一个中设置差分电路。半导体芯片包括设置在每个IO单元区域之上并且电连接到差分电路的非反相端子的非反相焊盘电极。半导体芯片包括设置在每个IO单元区域上方并连接到差分电路的反相端的反相焊盘电极。

9. 发明申请

US20120068306A1 SEMICONDUCTOR PACKAGE INCLUDING DECOUPLING SEMICONDUCTOR CAPACITOR 审中-公开
标题翻译：半导体封装，包括解耦半导体电容器
公开(公告)号：US20120068306A1
公开(公告)日：2012-03-22
申请号：US13230875
申请日：2011-09-13
申请人： Sang-Sub SONG , Sung-Hoon Chun , Sang-Ho An , Joon-Young Oh , Dong-Ok Kwak
发明人： Sang-Sub SONG , Sung-Hoon Chun , Sang-Ho An , Joon-Young Oh , Dong-Ok Kwak
IPC分类号： H01L27/08
CPC分类号： H01L23/50 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L28/60 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05669 , H01L2224/06139 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package includes a packaging substrate including a first bond finger and a second bond finger, a first semiconductor chip mounted on the packaging substrate, and including a first chip pad and a second chip pad, the first bond finger being electrically connected to the first chip pad by a first bonding wire, and the second bond finger being electrically connected to the second chip pad by a second bonding wire, and a first decoupling semiconductor capacitor mounted on the first semiconductor chip, and including a first capacitor pad, the first capacitor pad being electrically connected to the second chip pad.
摘要翻译：半导体封装包括包括第一键合指状物和第二键合指状物的封装衬底，安装在封装衬底上的第一半导体芯片，并且包括第一芯片焊盘和第二芯片焊盘，第一键合指状电连接到第一键并且所述第二接合指状物通过第二接合线电连接到所述第二芯片焊盘，以及安装在所述第一半导体芯片上的第一解耦半导体电容器，并且包括第一电容器焊盘，所述第一电容器焊盘电连接到第二芯片焊盘。

10. 发明公开

EP2930745A2 I/O cell configuration for a differential amplifier on a semiconductor chip and semiconductor package including the same 审中-公开
标题翻译：用于在半导体芯片上的差分放大器以及那些含有半导体封装的输入/输出单元布置
公开(公告)号：EP2930745A2
公开(公告)日：2015-10-14
申请号：EP15156566.0
申请日：2015-02-25
申请人： Kabushiki Kaisha Toshiba
发明人： Fukuda, Shohei
IPC分类号： H01L23/485 , H01L23/49 , H03K19/0185 , H03K19/177
CPC分类号： H01L24/49 , G06F17/5068 , H01L23/481 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/05554 , H01L2224/06133 , H01L2224/06135 , H01L2224/06139 , H01L2224/48011 , H01L2224/48091 , H01L2224/49431 , H01L2224/49433 , H01L2924/00014 , H01L2924/386 , H03K19/018514 , H03K19/17744 , H01L2224/45099 , H01L2224/05599
摘要： The semiconductor package includes a semiconductor chip (1) mounted on the base substrate (2). The semiconductor chip includes a core region disposed in a center part of the semiconductor chip, an internal circuit being provided in the core region. The semiconductor chip (1) includes a plurality of IO cell regions (I01, I02, I03) disposed in a line along a side of the semiconductor chip (1), a differential circuit being provided in each of the plurality of IO cell regions (I01, I02, I03). The semiconductor chip (1) includes a non-inverting pad electrode (P1, P2, P3) disposed above each of the IO cell regions (I01, I02, I03) and electrically connected to a non-inverting terminal of the differential amplifying circuit (A1, A2, A3). The semiconductor chip includes an inverting pad electrode (N1, N2, N3) disposed above each of the IO cell regions (I01, I02, I03) and connected to an inverting terminal of the differential circuit. A first set of a first non-inverting pad electrode (P1) and a first inverting pad electrode (N1) is disposed above a first IO cell region (I01) of the plurality of IO cell regions (I01, I02, I03), and the first set is disposed so that the first non-inverting pad electrode (P1) and the first inverting pad electrode (N1) are disposed along a first line (Y1) along the side (1a) of the semiconductor chip (1); andwherein a second set of a second non-inverting pad electrode (P2) and a second inverting pad electrode (N2) is disposed above a second IO cell region (102) of the plurality of IO cell regions (I01, I02, I03), and the second set is disposed so that the second non-inverting pad electrode (P2) and the second inverting pad electrode (N2) are disposed along a second line (Y2) along the side (1a) of the semiconductor chip (1).
摘要翻译：半导体封装包括：安装在所述基底基板（2）的半导体芯片（1）。该半导体芯片包括在半导体芯片的中心部分设置在芯区域中，以在核心区域被提供内部电路。在半导体芯片（1）包括：IO单元区域（I01，I02，I03），设置（在一个线沿（1），在各IO单元区域的多个被提供的差分电路的半导体芯片的一侧上的多个 I01，I02，I03）。在半导体芯片（1）具备上述各IO单元区域的（I01，I02，I03），并电连接到所述差分放大电路的非反相端子（设置在非反相焊盘电极（P1，P2，P3） A1，A2，A3）。该半导体芯片包括在反转上述各IO单元区域（I01，I02，I03）的设置，并且在反相差分电路的端子连接到焊盘电极（N1，N2，N3）。第一组的第一非反相焊盘电极（P1）和第一反相焊盘电极（N1）IO单元区域（I01，I02，I03）的多个第一IO单元区域（I01）以上是设置，并象第一非反相焊盘电极（P1）和所述第一反相焊盘电极（N1）沿着所述半导体芯片（1）的侧部（1A）的第一线（Y1）被布置在第一组设置; 并且其中的第二组的第二非反相焊盘电极（P2）和第二反相焊盘电极（N2）被IO单元区域的所述多个第二IO单元区域（102）的正上方（I01，I02，I03）并且象在第二非反相焊盘电极（P2）和所述第二反相焊盘电极（N2）沿半导体芯片（1）的沿侧（1a）的第二线（Y2）被布置在第二组设置。

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