专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0644479A2 Multiple resonant tunneling circuits for signed digit multi-valued logic operations 失效
标题翻译：使用带有标有数字多值逻辑操作的多个谐振隧道效应的电路。
公开(公告)号：EP0644479A2
公开(公告)日：1995-03-22
申请号：EP94303700.2
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H. , Micheel, Lutz J.
IPC分类号： G06F7/49 , H03K23/00 , H01L29/73
CPC分类号： B82Y10/00 , G06F7/4824
摘要： Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions. In one form of the invention, an adder for calculating the sum of two numbers represented by signed digit range-3 base-4 words is constructed from summation circuits (40) which add corresponding digits of input words X and Y to form digit sums S i , signed range-5 to signed range-3 converter circuits (42) which use multi-level folding circuits (64) connected by voltage dividers to decompose the digit sums into an interim sum and carry digit, and a second set of summation circuits (40) which add interim sum and carry digits to produce the digits of the result. Preferably, the sum is likewise represented by a signed digit range-3 base-4 word. Preferably, the multi-level folding circuits contain resonant tunneling transistors (e.g. bipolar transistors with multiple-peak resonant tunneling diodes (52) integrated into the emitter).
摘要翻译：含共振隧穿器件电路是游离缺失盘它提供了实现超高密度，超高性能的多值逻辑运算集成电路显著的优势。与谐振隧穿器件上实现多值逻辑电路可实现增加的速度和密度超过在常规IC技术实现的二进制电路和多值电路由于多个二进制位由硬件架构，这使得使用具有多个负跨区域的设备非常有效地处理。在本发明的一种形式中，向加法器用于计算由签署数字范围-3-基4个字表示的两个数之和是从求和电路40加输入字X和Y对应的数字，以形成数字求和硅建造，签署范围-5至符号范围-3转换器电路42，其使用多级折叠电路64由分压器连接到分解的数字总和成临时总和和进位数字，而第二组求和电路40，其添加临时总和和进位的数字产生结果的数字。优选地，所述总和被类似地由一个带符号的数字范围-3-基-4-字代表。优选地，多级折叠电路包含谐振隧穿晶体管（与集成到发射器的多峰共振隧穿二极管52 E.G.双极型晶体管）。

2. 发明公开

EP0774839A3 Negative resistance element for multivalue to binary conversion 失效
标题翻译：用于将多电平信号转换成二进制信号的负电阻元件
公开(公告)号：EP0774839A3
公开(公告)日：1999-08-25
申请号：EP96116660.0
申请日：1996-10-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Seabaugh, Alan C. , Taddiken, Albert H. , Obeid, Iyad
IPC分类号： H03M5/16
CPC分类号： B82Y10/00 , H03M5/16
摘要： A circuit that can form the core element for analog-to-digital convertors and multi-valued to binary converter circuits is disclosed. The circuit has an input transistor 20 coupled to receive an input signal V IN . A first negative-resistance element 22, RTD couples between the output electrode V OUT of the input transistor 20 and a positive voltage source. A second negative-resistance element 3RTD couples between the input transistor 20 and ground. The peak to valley current ratio of the first negative-resistance element 22,RTD is selected to be less than the peak to valley current ratio of the second negative-resistance element 3RTD. The circuit functions to convert inputs at varying voltages (multi-valued) to two levels at the output V OUT .

3. 发明公开

EP0643489A1 Binary converter 失效
标题翻译： Binärkonverter。
公开(公告)号：EP0643489A1
公开(公告)日：1995-03-15
申请号：EP94303701.0
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H.
IPC分类号： H03M7/02 , H03M5/20
CPC分类号： G06F7/5013 , B82Y10/00 , H03M5/20 , H03M7/02
摘要： Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary representation. In one form of the invention, a number represented by a range-4 base-2 word is converted into a conventional binary word (range-2 base-2) having the same value. The conversion is accomplished by a series of decomposition stages 53 , each decomposition stage 53 producing an interim range-4 base-2 word and a binary digit, which becomes one of the digits of the binary output word. Preferably, the decomposition at each stage is accomplished by a set of range-4 base-2 to binary converters 50 , each of which operates on a single digit of the interim word. Preferably, summation circuits 52 sum outputs of adjoining range-4 base-2 converters 50 to form the new interim word. The least significant digit of the output of the decomposition stage becomes a digit of the output binary word. Preferably, the range-4 base-2 to binary converters 50 are multi-level folding circuits 54 connected by a voltage divider. Preferably, the multi-level folding circuits contain multiple-peak resonant tunneling transistors 56 (e.g. an FET 58 and a multiple-peak resonant tunneling diode 60 ) which exhibit multiple negative differential transconductance. The novel circuits presented allow the results of multivalued logic operations to be translated to binary representation at very high speed. Additionally, because they make use of resonant tunneling devices, the novel converter circuits described herein may be fabricated with very few components.
摘要翻译：多个谐振隧穿装置为实现将多值数字系统表示的值有效地转换为常规二进制表示的电路提供了显着的优点。在本发明的一种形式中，由范围-4基2字表示的数字被转换成具有相同值的常规二进制字（范围-2 base-2）。转换通过一系列分解阶段53完成，每个分解阶段53产生中间范围-4基2字和二进制数字，二进制数字成为二进制输出字的数字之一。优选地，每个阶段的分解由一组范围-4的基底2到二进制转换器50来实现，每个变换器50对临时字的单个数字进行操作。优选地，求和电路52对相邻的范围-4基2转换器50的输出求和，以形成新的临时字。分解阶段的输出的最低有效位成为输出二进制字的数字。优选地，范围-4基极2到二进制转换器50是通过分压器连接的多电平折叠电路54。优选地，多电平折叠电路包含展现多个负差分跨导的多峰谐振隧穿晶体管56（例如，FET58和多峰谐振隧穿二极管60）。所提出的新颖电路允许将多值逻辑运算的结果以非常高的速度转换为二进制表示。此外，由于它们利用谐振隧穿装置，本文所述的新颖的转换器电路可以用极少的部件制造。

4. 发明公开

EP0774839A2 Negative resistance element for multivalue to binary conversion 失效
标题翻译： Element mit negativem Widerstand zum Konvertieren mehrstufiger Signale inbinäreSignale
公开(公告)号：EP0774839A2
公开(公告)日：1997-05-21
申请号：EP96116660.0
申请日：1996-10-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Seabaugh, Alan C. , Taddiken, Albert H. , Obeid, Iyad
IPC分类号： H03M5/16
CPC分类号： B82Y10/00 , H03M5/16
摘要： A circuit that can form the core element for analog-to-digital convertors and multi-valued to binary converter circuits is disclosed. The circuit has an input transistor 20 coupled to receive an input signal V IN . A first negative-resistance element 22, RTD couples between the output electrode V OUT of the input transistor 20 and a positive voltage source. A second negative-resistance element 3RTD couples between the input transistor 20 and ground. The peak to valley current ratio of the first negative-resistance element 22,RTD is selected to be less than the peak to valley current ratio of the second negative-resistance element 3RTD. The circuit functions to convert inputs at varying voltages (multi-valued) to two levels at the output V OUT .
摘要翻译：公开了可以形成模数转换器和多值二进制转换器电路的核心元件的电路。该电路具有耦合以接收输入信号VIN的输入晶体管20。第一负电阻元件22，RTD耦合在输入晶体管20的输出电极VOUT和正电压源之间。第二负电阻元件3RTD耦合在输入晶体管20和地之间。选择第一负电阻元件22，RTD的峰谷电流比小于第二负电阻元件3RTD的峰谷电流比。该电路用于将输入电压（多值）转换为输出VOUT上的两个电平。

5. 发明公开

EP0644480A2 Multiple resonant tunneling circuits for positive digit multi-valued logic operations 失效
标题翻译：电路中使用，用于与正数多值逻辑操作的多个共振隧道效应。
公开(公告)号：EP0644480A2
公开(公告)日：1995-03-22
申请号：EP94303702.8
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H.
IPC分类号： G06F7/49 , H03K23/00 , H01L29/73
CPC分类号： B82Y10/00 , G06F7/49 , G06F2207/4828
摘要： Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits (40) which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits (42) , then three-input summation circuits (44) sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits (56) which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors (54) . Ripple carries are eliminated and the speed of the adder is independent of input word width.
摘要翻译：多个谐振隧穿器件为实现超高密度，超高性能多值逻辑运算的集成电路显著优点。多值逻辑加法器盘游离缺失，worin由正数字基-M范围-N字表示两个数字由两输入求和电路40，其总和CORRESPONDING位数，那么数字总和按范围-7多值分解成二进制表示被添加二进制转换器电路42，然后三输入求和电路的二进制表示的44个适当总和比特来计算正数字基-2-范围-4字，其值是两个数字的总和的数字。优选地，所述分解到二进制表示通过由分压器电路连接的多值折叠电路56执行的。优选地，该多值折叠电路包含多峰共振隧穿晶体管54纹波携带被消除并且加法器的速度是独立于输入字的宽度。

6. 发明公开

EP0344925A2 Superconductively loaded semiconductor logic device 失效
标题翻译： Logische Halbleitervorrichtung mit supraleitender Ladung。
公开(公告)号：EP0344925A2
公开(公告)日：1989-12-06
申请号：EP89304595.5
申请日：1989-05-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H. , Yuan, Han-Tzong
IPC分类号： H03K19/195 , H03K19/094 , H03K17/92
CPC分类号： H03K3/38 , H03K3/356052 , H03K19/094 , H03K19/195
摘要： A circuit having a first logic inverter. The inverter comprises an input device (12) having an electrode (14) for receiving an input signal, a first terminal (16) for connection to a reference potential and a second terminal (18) for providing an output signal. A load device (22) formed of superconductive material is positioned between the second terminal (18) and a connection point (24) for receiving a second voltage potential. The superconducting device (22) operates as a non-linear load between the connection point (24) and the second terminal (18) when conducting a current in excess of a critical current density J C .
摘要翻译：一种具有第一逻辑反相器的电路。逆变器包括具有用于接收输入信号的电极（14）的输入装置（12），用于连接到参考电位的第一端子（16）和用于提供输出信号的第二端子（18）。由超导材料形成的负载装置（22）位于第二端子（18）和用于接收第二电压电位的连接点（24）之间。当超过临界电流密度JC的电流时，超导装置（22）作为连接点（24）和第二端子（18）之间的非线性负载工作。

7. 发明公开

EP0644480A3 Multiple resonant tunneling circuits for positive digit multi-valued logic operations 失效
标题翻译：电路中使用，用于与正数多值逻辑操作的多个共振隧道效应。
公开(公告)号：EP0644480A3
公开(公告)日：1996-12-11
申请号：EP94303702.8
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H.
IPC分类号： G06F7/49 , H03K23/00 , H01L29/73
CPC分类号： B82Y10/00 , G06F7/49 , G06F2207/4828
摘要： Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits (40) which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits (42) , then three-input summation circuits (44) sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits (56) which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors (54) . Ripple carries are eliminated and the speed of the adder is independent of input word width.

8. 发明公开

EP0644479A3 Multiple resonant tunneling circuits for signed digit multi-valued logic operations 失效
标题翻译：使用带有标有数字多值逻辑操作的多个谐振隧道效应的电路。
公开(公告)号：EP0644479A3
公开(公告)日：1996-12-11
申请号：EP94303700.2
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H. , Micheel, Lutz J.
IPC分类号： G06F7/49 , H03K23/00 , H01L29/73
CPC分类号： B82Y10/00 , G06F7/4824
摘要： Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions. In one form of the invention, an adder for calculating the sum of two numbers represented by signed digit range-3 base-4 words is constructed from summation circuits (40) which add corresponding digits of input words X and Y to form digit sums S i , signed range-5 to signed range-3 converter circuits (42) which use multi-level folding circuits (64) connected by voltage dividers to decompose the digit sums into an interim sum and carry digit, and a second set of summation circuits (40) which add interim sum and carry digits to produce the digits of the result. Preferably, the sum is likewise represented by a signed digit range-3 base-4 word. Preferably, the multi-level folding circuits contain resonant tunneling transistors (e.g. bipolar transistors with multiple-peak resonant tunneling diodes (52) integrated into the emitter).

9. 发明授权

EP0344925B1 Superconductively loaded semiconductor logic device 失效
标题翻译：具有超导电荷逻辑半导体装置。
公开(公告)号：EP0344925B1
公开(公告)日：1994-08-03
申请号：EP89304595.5
申请日：1989-05-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H. , Yuan, Han-Tzong
IPC分类号： H03K19/195 , H03K19/094 , H03K17/92
CPC分类号： H03K3/38 , H03K3/356052 , H03K19/094 , H03K19/195

10. 发明公开

EP0344925A3 Superconductively loaded semiconductor logic device 失效
标题翻译：超级加载半导体逻辑器件
公开(公告)号：EP0344925A3
公开(公告)日：1990-08-08
申请号：EP89304595.5
申请日：1989-05-05
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H. , Yuan, Han-Tzong
IPC分类号： H03K19/195 , H03K19/094 , H03K17/92
CPC分类号： H03K3/38 , H03K3/356052 , H03K19/094 , H03K19/195
摘要： A circuit having a first logic inverter. The inverter comprises an input device (12) having an electrode (14) for receiving an input signal, a first terminal (16) for connection to a reference potential and a second terminal (18) for providing an output signal. A load device (22) formed of superconductive material is positioned between the second terminal (18) and a connection point (24) for receiving a second voltage potential. The superconducting device (22) operates as a non-linear load between the connection point (24) and the second terminal (18) when conducting a current in excess of a critical current density J C .
摘要翻译：一种具有第一逻辑反相器的电路。逆变器包括具有用于接收输入信号的电极（14）的输入装置（12），用于连接到参考电位的第一端子（16）和用于提供输出信号的第二端子（18）。由超导材料形成的负载装置（22）位于第二端子（18）和用于接收第二电压电位的连接点（24）之间。当超过临界电流密度JC的电流时，超导装置（22）作为连接点（24）和第二端子（18）之间的非线性负载工作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式