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1. 发明专利

AU636818B2 METHODS AND APPARATUS FOR MATERIAL DEPOSITION 未知
公开(公告)号：AU636818B2
公开(公告)日：1993-05-06
申请号：AU4846990
申请日：1989-12-27
申请人： SYMETRIX CORPORATION
发明人： LARRY D. MCMILLAN , CARLOS A. PAZ DE ARAUJO
IPC分类号： C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/50 , C23C16/515 , C23C16/52 , C23C18/12 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316
摘要： Methods and apparatus for depositing thin films of complex (compound) materials, including ferroelectrics, superconductors, and materials with high dielectric constants by photo/plasma-enhanced chemical vapor deposition from stabilized compound sources. Multiple heating (10, 12) and/or spectral energy sources (8) are used for applying high energy, rapid thermal pulses in a precise timed sequence. Sol-gels of compound sources are ultrasonically atomized before being introduced to a deposition chamber (2).

2. 发明专利

TWI301271B 鐵電非揮發性記憶體及鐵電非揮發性記憶體之讀取方法 FERROELECTRIC NON-VOLATILE MEMORY AND READING METHOD THEREOF 失效
简体标题：铁电非挥发性内存及铁电非挥发性内存之读取方法 FERROELECTRIC NON-VOLATILE MEMORY AND READING METHOD THEREOF
公开(公告)号：TWI301271B
公开(公告)日：2008-09-21
申请号：TW092112308
申请日：2003-05-06
申请人：西門特克斯公司 SYMETRIX CORPORATION , 艾歐塔科技有限公司 IOTA TECHNOLOGY, INC.
发明人：何宇明湯姆 IU MENG TOM HO
IPC分类号： G11C
CPC分类号： G11C11/22
摘要：一種鐵電記憶體(436)包括一位元線對(102,104),平行
且位於位元線間之一驅動線對(103),及一關聯之記憶體胞
元(100)。該記憶體胞元包括兩個鐵電電容器(106,108),各
電容器係經由電晶體(105,109)連接至該等位元線之一,且
各電容器同時經由電晶體(107)連接至該驅動線。所有三個
電晶體之閘極(123,126,128)係連接至和位元線及驅動線
垂直之字元線(101),使得在字元線未被選擇時,電容器被
完全絕緣而不受任何干擾。具有三個位元線(519,516,518)
輸入之感知放大器(502)比較該胞元位元線和二虛位元線
(226,228)驅動之信號。需電容器之邏輯狀態在每一週期改
變,以防止留下印記或產生疲乏。記憶體胞元係以在不同鐵
電極化狀態下,區分鐵電電容器的不同電容量之非破壞性讀
出方法而讀取。
简体摘要：一种铁电内存(436)包括一比特线对(102,104),平行且位于比特线间之一驱动线对(103),及一关联之内存胞元(100)。该内存胞元包括两个铁电电容器(106,108),各电容器系经由晶体管(105,109)连接至该等比特线之一,且各电容器同时经由晶体管(107)连接至该驱动线。所有三个晶体管之闸极(123,126,128)系连接至和比特线及驱动线垂直之字符线(101),使得在字符线未被选择时,电容器被完全绝缘而不受任何干扰。具有三个比特线(519,516,518) 输入之感知放大器(502)比较该胞元比特线和二虚比特线 (226,228)驱动之信号。需电容器之逻辑状态在每一周期改变,以防止留下印记或产生疲乏。内存胞元系以在不同铁电极化状态下,区分铁电电容器的不同电容量之非破坏性读出方法而读取。

3. 发明申请

WO2004076991A2 PYROELECTRIC SENSOR 审中-公开
标题翻译：光电传感器
公开(公告)号：WO2004076991A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/005100
申请日：2004-02-20
申请人： DELPHI TECHNOLOGIES, INC. , SYMETRIX CORPORATION , MANTESE, Joseph, V. , SCHUBRING, Norman, W. , MICHELI, Adolph, L. , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D. , CELINSKA, Jolanta
发明人： MANTESE, Joseph, V. , SCHUBRING, Norman, W. , MICHELI, Adolph, L. , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D. , CELINSKA, Jolanta
IPC分类号： G01J
CPC分类号： G01J5/34
摘要： A ferroelectric/pyroelectric sensor employs a technique for determining a charge output of a ferroelectric scene element of the sensor by measuring the hysteresis loop output of the scene element several times during a particular time frame for the same temperature. An external AC signal is applied to the ferroelectric scene element to cause the hysteresis loop output from the element to switch polarization. Charge integration circuitry, such as a combination output capacitor and operational amplifier, is employed to measure the charge from the scene element. Preferably, the ferroelectric of the scene element is made of an economical and responsive strontium bismuth tantalate, SBT, or derivative thereof, disposed directly between top and bottom electrodes. Because of the frequency characteristics of the sensor, created by the external AC signal, the element need not be thermally isolated from the silicon substrate by a traditional air bridge, which is difficult to manufacture, and instead is preferably thermally isolated by spin-on-glass, SOG. To prevent saturation of an output signal voltage of the sensor by excessive charge accumulation in an output capacitor, the sensor preferably has a reference element configured electrically in parallel with the scene element. When the voltage of the AC signal is negative the output capacitor is discharged by flowing current through the reference element thus interrogating the polarization of the reference element which is compared to and subtracted from the polarization of the scene element for each cycle. The polarization difference measured for each cycle over a set time period are summed by an integrating amplifier to produce a signal output voltage.
摘要翻译：铁电/热电传感器采用用于通过在相同温度的特定时间段内多次测量场景元件的磁滞回线输出来确定传感器的铁电场景元件的电荷输出的技术。外部交流信号被施加到铁电场景元件以使得从元件输出的磁滞回线转换偏振。采用诸如组合输出电容器和运算放大器的电荷积分电路来测量场景元件中的电荷。优选地，场景元件的铁电体由直接设置在顶部和底部电极之间的经济且响应的钽酸铋铋钡，或其衍生物制成。由于由外部AC信号产生的传感器的频率特性，该元件不需要通过难以制造的传统空气桥与硅衬底热隔离，而是优选地通过旋转隔离热隔离，玻璃，SOG。为了通过输出电容器中的过度电荷积累来防止传感器的输出信号电压的饱和，传感器优选地具有与场景元件电并联配置的参考元件。当AC信号的电压为负时，输出电容器通过流过参考元件的电流而被放电，从而询问参考元件的偏振，该参考元件的偏振与每个周期的场景元素的偏振相比较和减去。在设定的时间周期内对每个周期测量的偏振差由积分放大器相加以产生信号输出电压。

4. 发明申请

WO2003096352A2 FERROELECTRIC MEMORY 审中-公开
标题翻译：电磁记忆
公开(公告)号：WO2003096352A2
公开(公告)日：2003-11-20
申请号：PCT/US2003/014015
申请日：2003-05-05
申请人： SYMETRIX CORPORATION , IOTA TECHNOLOGY, INC. , HO, Iu-Meng, Tom
发明人： HO, Iu-Meng, Tom
IPC分类号： G11C
CPC分类号： G11C11/22
摘要： A ferroelectric memory (436) including a bit line pair (102, 104), a drive line (103) parallel to and located between the bit lines, and an associated memory cell (100). The memory cell includes two ferroelectric capacitors (106, 108), each capacitor connected to one of said bit lines via a transistor (105, 109), and each capacitor also connected to the drive line via a transistor (107). The gates (123, 136, 128) of all three of the transistors are connected to a word line (101) perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. A sense amplifier (502) with three bit line inputs (519, 516, 518) compares the cell bit line with a signal derived from the two dummy bit lines (226, 228). The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.
摘要翻译：包括位线对（102,104），平行于并位于位线之间的驱动线（103）和相关联的存储单元（100）的铁电存储器（436）。存储单元包括两个铁电电容器（106,108），每个电容器经由晶体管（105,109）连接到所述位线之一，并且每个电容器还经由晶体管（107）连接到驱动线路。所有三个晶体管的栅极（123,136,128）连接到垂直于位线和驱动线的字线（101），使得当字线未被选择时，电容器完全与任何打扰。具有三个位线输入（519,516,518）的读出放大器（502）将单元位线与从两个虚拟位线（226,228）导出的信号进行比较。以非破坏性读出方法读取存储单元，其区分不同铁电极化状态下的铁电电容器的不同电容。

5. 发明申请

WO2003049172A1 LANTHANIDE SERIES LAYERED SUPERLATTICE MATERIALS FOR INTEGRATED CIRCUIT APPLICATIONS 审中-公开
标题翻译：用于集成电路应用的LANTHANIDE系列层状超级材料
公开(公告)号：WO2003049172A1
公开(公告)日：2003-06-12
申请号：PCT/US2002/029325
申请日：2002-09-17
申请人： SYMETRIX CORPORATION
发明人： PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D. , SOLAYAPPAN, Narayan
IPC分类号： H01L21/316
CPC分类号： C23C18/1216 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/482 , C23C16/52 , C23C18/1225 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/60 , Y10T428/24926
摘要： An integrated circuit (40) includes a layered superlattice material (57) including one or more of the elements cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. These elements may either be A-site elements or superlattice generator elements in the layered superlattice material. In one embodiment, one or more of these elements substitute for bismuth in a bismuth layered material. They also are preferably used in combination with one or more of the following elements: strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, thallium, oxygen, chlorine, and fluorine. Some of these materials are ferroelectrics that crystallize at relatively low temperatures. Others are high dielectric constant materials that do not degrade or break down over long periods of use.
摘要翻译：集成电路（40）包括层状超晶格材料（57），其包括铈，镨，钕，ium，钐，铕，钆，铽，镝，钬，铒，ium，镱和镥中的一种或多种元素。这些元素可以是分层超晶格材料中的A位元素或超晶格发生器元件。在一个实施方案中，这些元素中的一种或多种在铋层状材料中代替铋。它们还优选与以下元素中的一种或多种组合使用：锶，钙，钡，铋，镉，铅，钛，钽，铪，钨，铌，锆，铋，钪，钇，镧，锑，铬，铊，氧，氯和氟。这些材料中的一些是在较低温度下结晶的铁电体。其他的是高介电常数材料，不会在长期使用中降解或分解。

6. 发明申请

WO2003049147A2 BARRIER LAYERS FOR PROTECTING METAL OXIDES FROM HYDROGEN DEGRADATION 审中-公开
标题翻译：用于从氢降解中保护金属氧化物的阻挡层
公开(公告)号：WO2003049147A2
公开(公告)日：2003-06-12
申请号：PCT/US2002/037694
申请日：2002-11-22
申请人： SYMETRIX CORPORATION , SOLAYAPPAN, Narayan , CELINSKA, Jolanta , JOSHI, Vikram , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
发明人： SOLAYAPPAN, Narayan , CELINSKA, Jolanta , JOSHI, Vikram , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： H01L
CPC分类号： H01L28/57 , H01L23/642 , H01L2924/0002 , H01L2924/00
摘要： A hydrogen diffusion barrier (120, 160, 204, 227, 228, 284, 391, 724, 728) in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide (110, 216, 396, 240, 738), such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide, and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450°C or less. In some embodiments, a supplemental hydrogen barrier layer (229, 393) comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
摘要翻译：位于集成电路中的氢扩散阻挡层（120,160,204,227,228,384,391,724,728）被设置成阻止氢扩散到金属氧化物（110,216,396,240,408）的薄膜，738），例如集成电路中的铁电层状超晶格材料。氢扩散阻挡层包括以下化合物中的至少一种：钽酸锶，钽酸铋，氧化钽，氧化钛，氧化锆和氧化铝。氢阻挡层是无定形的，并且在450℃或更低的温度下通过MOCVD法制备。在一些实施例中，与所述氢扩散阻挡层相邻形成包括选自氮化硅和所述氢阻挡层材料之一的结晶形式的材料的补充氢阻挡层（229,393）。

7. 发明申请

WO2002025667A3 FERROELECTRIC MEMORY AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2002025667A3
公开(公告)日：2002-03-28
申请号：PCT/US2001/042288
申请日：2001-09-25
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , CHEN, Zheng , KATO, Yoshihisa , JOSHI, Vikram , LIM, Myoungho , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D. , SHIMADA, Yasuhiro , OTSUKI, Tatsuo
发明人： CHEN, Zheng , KATO, Yoshihisa , JOSHI, Vikram , LIM, Myoungho , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D. , SHIMADA, Yasuhiro , OTSUKI, Tatsuo
IPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

8. 发明申请

WO1997035315A1 ELECTRONIC MEMORY 审中-公开
标题翻译：电子内存
公开(公告)号：WO1997035315A1
公开(公告)日：1997-09-25
申请号：PCT/US1997003954
申请日：1997-03-14
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , DEVILBISS, Alan
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory cell (30) includes a ferroelectric capacitor (32) and a transistor (34) connected between one side of the capacitor and a bit line (53). A drive circuit (40) includes an operational amplifier (12) having an output, an inverting input, and a non-inverting input. A plate line (56) is connected between the other side (36) of the capacitor and the output. The non-inverting input is connected to a data-in line (47) through a first resistor (20) and to the bit line through a second resistor (21). The inverting input is connected to a constant voltage source (48) through a third resistor (22), and to the plate line (56) through a fourth resistor (23). A first buffer amplifier (82) is connected between the bit line and the second resistor, and a second buffer amplifier (84) is connected between the plate line and the fourth resistor.
摘要翻译：存储单元（30）包括连接在电容器的一侧和位线（53）之间的铁电电容器（32）和晶体管（34）。驱动电路（40）包括具有输出，反相输入和非反相输入的运算放大器（12）。板状线（56）连接在电容器的另一侧（36）和输出端之间。非反相输入端通过第一电阻器（20）连接到数据输入线（47），并通过第二电阻器（21）连接到位线。反相输入通过第三电阻器（22）连接到恒定电压源（48），并通过第四电阻器（23）连接到板极线路（56）。第一缓冲放大器（82）连接在位线和第二电阻器之间，第二缓冲放大器（84）连接在板线和第四电阻器之间。

9. 发明申请

WO1997034156A1 APPARATUS FOR MEASURING PARAMETERS OF AN ELECTRONIC DEVICE 审中-公开
标题翻译：用于测量电子设备参数的装置
公开(公告)号：WO1997034156A1
公开(公告)日：1997-09-18
申请号：PCT/US1997004568
申请日：1997-03-17
申请人： SYMETRIX CORPORATION , DEVILBISS, Alan
发明人： SYMETRIX CORPORATION
IPC分类号： G01R19/00
CPC分类号： G01R19/0023
摘要： A first terminal (791) of a device-under-measurement (DUM) is connected to a buffer amplifier (758) and to the inverting input (747) of an operational amplifier (754). A second terminal (792) of the DUM is connected to a buffer amplifier (756) having its output (796) connected to the non-inverting input (746) of the operational amplifier (754). The non-inverting input is also connected to the output (793) of a signal generator (760). The second terminal (792) is also connected to ground (767) through a programmable load circuit (762). A circuit (779) creates a feedback loop from the DUM and the load circuit (762) to the operational amplifier (754) to enable the amplifier to maintain a predetermined voltage across the DUM and to isolate the amplifier from current flow from the load circuit (762). An oscilloscope (766) is connected across the outputs (727, 796) of the buffer amplifiers (758, 757) and a computer (764) controls the signal generator (760) in response to a signal from the oscilloscope and also controls the load (762) via a load control circuit (765).
摘要翻译：被测器件（DUM）的第一端子（791）连接到缓冲放大器（758）和运算放大器（754）的反相输入端（747）。 DUM的第二端子（792）连接到其输出（796）连接到运算放大器（754）的非反相输入端（746）的缓冲放大器（756）。同相输入也连接到信号发生器（760）的输出（793）。第二端子（792）还通过可编程负载电路（762）连接到地（767）。电路（779）创建从DUM和负载电路（762）到运算放大器（754）的反馈回路，以使放大器能够在DUM两端保持预定电压，并将放大器与来自负载电路的电流隔离（762）。示波器（766）连接在缓冲放大器（758,757）的输出端（727,796）上，并且计算机（764）响应于来自示波器的信号控制信号发生器（760），并且还控制负载（762）经由负载控制电路（765）。

10. 发明申请

WO1997007546A1 METAL INSULATOR SEMICONDUCTOR STRUCTURE WITH POLARIZATION-COMPATIBLE BUFFER LAYER 审中-公开
标题翻译：具有极化兼容缓冲层的金属绝缘子半导体结构
公开(公告)号：WO1997007546A1
公开(公告)日：1997-02-27
申请号：PCT/US1996013310
申请日：1996-08-19
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION
发明人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION , AZUMA, Masamichi , PAZ DE ARAUJO, Carlos
IPC分类号： H01L29/51
CPC分类号： C23C18/14 , C04B35/62227 , C23C16/448 , C23C16/45561 , C23C18/1216 , C23C18/1225 , C23C18/1295 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L29/78391
摘要： An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxyde superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.
摘要翻译： MIS器件（20）包括半导体衬底（22），氮化硅缓冲层（24），铁电金属氧化物超晶格材料（26）和贵金属顶电极（28）。层状超晶格材料（26）优选为钽酸锶锶，铌酸铋锶或钽酸铋铌钽酸锶。根据优选的方法构造器件，其包括在沉积层状超晶格材料之前在半导体衬底上形成氮化硅。层状超晶格材料优选使用液体聚氧化烷基化的金属有机前体沉积，其在加热前体溶液时自发产生层状超晶格。在前体液体的干燥期间的紫外线曝光赋予最终晶体C轴取向，并且导致改善的薄膜电性能。

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