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1. 发明申请

WO2006115819A1 ELECTRONIC DIFFERENTIAL BUSES UTILIZING THE NULL STATE FOR DATA TRANSFER 审中-公开
标题翻译：使用数据传输空状态的电子差分业务
公开(公告)号：WO2006115819A1
公开(公告)日：2006-11-02
申请号：PCT/US2006/014017
申请日：2006-04-14
申请人： IOTA TECHNOLOGY, INC. , HO, Iu-Meng Tom
发明人： HO, Iu-Meng Tom
IPC分类号： G06F13/40
CPC分类号： G06F13/4072
摘要： An electronic data system comprising: a differential data system bus comprising true and complement signal wires; a write circuit for writing a Logic 0, a Logic 1 and a NULL state to the differential data system bus, wherein the NULL state is a state where Vdiff = 0; and a read circuit for reading the Logic 0, the Logic 1 and the NULL state from the the differential data system bus. In one embodiment, there are two differential data buses making a data bus pair, and at least one data bit is determined by an electronic state of the first bus and an electronic state of the second bus. In this embodiment, the write circuit is capable of placing each of the first and second data bus pairs in three electronic states for a total of nine possible electronic state combinations.
摘要翻译：一种电子数据系统，包括：包含真实和补码信号线的差分数据系统总线; 用于将逻辑0，逻辑1和空状态写入差分数据系统总线的写入电路，其中空状态是Vdiff = 0的状态; 以及用于从差分数据系统总线读取逻辑0，逻辑1和空状态的读取电路。在一个实施例中，存在两条形成数据总线对的差分数据总线，并且至少一个数据位由第一总线的电子状态和第二总线的电子状态确定。在该实施例中，写入电路能够将第一和第二数据总线对中的每一个放置在三个电子状态中，共有九个可能的电子状态组合。

2. 发明申请

WO2003096352A2 FERROELECTRIC MEMORY 审中-公开
标题翻译：电磁记忆
公开(公告)号：WO2003096352A2
公开(公告)日：2003-11-20
申请号：PCT/US2003/014015
申请日：2003-05-05
申请人： SYMETRIX CORPORATION , IOTA TECHNOLOGY, INC. , HO, Iu-Meng, Tom
发明人： HO, Iu-Meng, Tom
IPC分类号： G11C
CPC分类号： G11C11/22
摘要： A ferroelectric memory (436) including a bit line pair (102, 104), a drive line (103) parallel to and located between the bit lines, and an associated memory cell (100). The memory cell includes two ferroelectric capacitors (106, 108), each capacitor connected to one of said bit lines via a transistor (105, 109), and each capacitor also connected to the drive line via a transistor (107). The gates (123, 136, 128) of all three of the transistors are connected to a word line (101) perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. A sense amplifier (502) with three bit line inputs (519, 516, 518) compares the cell bit line with a signal derived from the two dummy bit lines (226, 228). The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.
摘要翻译：包括位线对（102,104），平行于并位于位线之间的驱动线（103）和相关联的存储单元（100）的铁电存储器（436）。存储单元包括两个铁电电容器（106,108），每个电容器经由晶体管（105,109）连接到所述位线之一，并且每个电容器还经由晶体管（107）连接到驱动线路。所有三个晶体管的栅极（123,136,128）连接到垂直于位线和驱动线的字线（101），使得当字线未被选择时，电容器完全与任何打扰。具有三个位线输入（519,516,518）的读出放大器（502）将单元位线与从两个虚拟位线（226,228）导出的信号进行比较。以非破坏性读出方法读取存储单元，其区分不同铁电极化状态下的铁电电容器的不同电容。

3. 发明申请

WO2007064811A1 ELECTRONIC MEMORY WITH BINARY STORAGE ELEMENTS 审中-公开
标题翻译：具有二进制存储元件的电子存储器
公开(公告)号：WO2007064811A1
公开(公告)日：2007-06-07
申请号：PCT/US2006/045874
申请日：2006-12-01
申请人： IOTA TECHNOLOGY, INC. , HO, Iu-Meng, Tom
发明人： HO, Iu-Meng, Tom
IPC分类号： G11C11/56
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/16 , G11C11/22 , G11C11/4094 , G11C11/4097 , G11C11/5607 , G11C11/5621 , G11C11/565 , G11C11/5657 , G11C11/5678 , G11C13/0004 , G11C16/0408 , G11C16/0416 , G11C16/0441 , G11C16/0491 , G11C2211/4013 , G11C2211/5641 , H01L29/785
摘要： An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
摘要翻译：使用真实和互补双位线和双二进制存储元件的电子存储器单元架构，其包括具有四个二进制存储元件的存储器单元对，每个存储器单元对能够存在多达十六个电子存储器状态。通常用于存储两个真实和互补数据位的四个二进制存储元件用于存储两个，三个或四个数据位，这取决于允许的噪声容限和位宽选择。存储器可以是铁电存储器FeRAM，闪速存储器，ROM，动态存储器DRAM，OUM，MRAM，NAND存储器或NOR存储器。

4. 发明申请

WO2003096352A3 FERROELECTRIC MEMORY 审中-公开
公开(公告)号：WO2003096352A3
公开(公告)日：2003-11-20
申请号：PCT/US2003/014015
申请日：2003-05-05
申请人： SYMETRIX CORPORATION , IOTA TECHNOLOGY, INC. , HO, Iu-Meng, Tom
发明人： HO, Iu-Meng, Tom
IPC分类号： G11C11/22
摘要： A ferroelectric memory (436) including a bit line pair (102, 104), a drive line (103) parallel to and located between the bit lines, and an associated memory cell (100). The memory cell includes two ferroelectric capacitors (106, 108), each capacitor connected to one of said bit lines via a transistor (105, 109), and each capacitor also connected to the drive line via a transistor (107). The gates (123, 136, 128) of all three of the transistors are connected to a word line (101) perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. A sense amplifier (502) with three bit line inputs (519, 516, 518) compares the cell bit line with a signal derived from the two dummy bit lines (226, 228). The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.

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