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1. 发明专利

AU4798793A Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration 未知
公开(公告)号：AU4798793A
公开(公告)日：1994-03-03
申请号：AU4798793
申请日：1993-08-05
申请人： MONOLITHIC SYSTEM TECHNOLOGY INC
发明人： LEUNG WING Y , HSU FU-CHIEH
IPC分类号： G06F12/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/00 , G06F13/40 , G11C29/00 , G11C29/04 , G11C29/48 , H01L21/66 , H01L27/02 , H04L5/14 , H04L25/02 , G11C13/00 , G11C8/00 , G01R31/02 , G06F1/12 , G06F11/16
摘要： A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.

2. 发明申请

WO2007089558A2 METHOD TO INCREASE CHARGE RETENTION OF NON-VOLATILE MEMORY MANUFACTURED IN A SINGLE-GATE LOGIC PROCESS 审中-公开
标题翻译：增加在单门逻辑过程中制造的非易失性存储器的充电保持的方法
公开(公告)号：WO2007089558A2
公开(公告)日：2007-08-09
申请号：PCT/US2007/002118
申请日：2007-01-25
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： FANG, Gang-feng , SINITSKY, Dennis , LEUNG, Wingyu
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
摘要翻译：具有增加的电荷保持的非易失性存储单元在与使用单栅极常规逻辑工艺的逻辑器件相同的衬底上制造。在NVM单元的浮动栅极上形成硅化物阻挡电介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

3. 发明申请

WO2006057794A2 TRANSPARENT ERROR CORRECTING MEMORY THAT SUPPORTS PARTIAL-WORD WRITE 审中-公开
标题翻译：透明错误修正支持部分字写入的记忆
公开(公告)号：WO2006057794A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040087
申请日：2005-11-03
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu
发明人： LEUNG, Wingyu
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The read data word is corrected in response to the associated error correction bits, thereby creating a corrected data word. The corrected data word is merged with a write data word, thereby creating a merged write data word. Write error correction bits are generated in response to the merged write data word, and the merged write data word and write error correction bits are written to the memory array. The word line and the plurality of sense amplifiers remain enabled from the reading operation through the write operation, thereby speeding up the partial-word write operation.
摘要翻译：在存储器系统中执行高速部分字写入操作。首先，从存储器阵列读取包括数据字和相关联的纠错位的纠错码（ECC）字。在该读取操作期间，字线和多个读出放大器被使能。响应于相关联的纠错位来校正读取的数据字，由此创建校正的数据字。校正的数据字与写入数据字合并，从而创建合并的写入数据字。响应于合并的写入数据字产生写入纠错位，并且将合并的写入数据字和写入错误校正位写入存储器阵列。通过写入操作，字线和多个读出放大器从读取操作保持使能，从而加速部分字写入操作。

4. 发明申请

WO2003042826A3 ERROR CORRECTING MEMORY AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2003042826A3
公开(公告)日：2003-05-22
申请号：PCT/GB2002/005123
申请日：2002-11-13
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC , FREEMAN, Jacqueline, Carol
发明人： LEUNG, Wingyu , HSU, Fu-Chieh
IPC分类号： G06F11/10
摘要： A memory device that uses error correction code (ECC) circuitry to improve the reliability of the memory device in view of single-bit errors caused by hard failure or soft error. A write buffer is used to post write data, so that ECC generation and memory write array operation can be carried out in parallel. As a result there is no penalty in write latency or memory cycle time due to ECC generation. A write-back buffer is used to post corrected ECC words during read operations, so that write-back of corrected ECC words does not need to take place during the same cycle that data is read. Instead, write-back operations are performed during idle cycles when no external memory access is requested, such that the write back operation does not impose a penalty on memory cycle time or affect memory access latency.

5. 发明申请

WO2002089140A2 METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING MULTIPLE CLOCK DIVISION 审中-公开
标题翻译：使用多个时钟段在DRAM设备中完全隐藏刷新操作的方法和装置
公开(公告)号：WO2002089140A2
公开(公告)日：2002-11-07
申请号：PCT/GB2002/001935
申请日：2002-04-26
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , FREEMAN, Jacqueline, Carol
发明人： LEUNG, Wingyu , SIM, Jae-Kwang
IPC分类号： G11C
CPC分类号： G11C11/005 , G11C7/22 , G11C11/406 , G11C11/40618
摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signalling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.
摘要翻译：一种用于处理需要周期性刷新操作的DRAM阵列或其它存储器阵列的刷新的方法和装置，使得刷新不需要显式控制信号，也不需要在存储器阵列与外部存取客户端之间的握手通信。该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。实现时钟分配方案，以允许在N个连续时钟周期内执行N个外部访问和一个刷新操作。

6. 发明申请

WO2002069344A3 METHOD AND APPARATUS FOR FORCING IDLE CYCLES TO ENABLE REFRESH OPERATIONS IN A SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：WO2002069344A3
公开(公告)日：2002-09-06
申请号：PCT/US2002/004439
申请日：2002-02-12
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： LEUNG, Wingyu
IPC分类号： G11C11/406
摘要： Method and apparatus for operating a memory system having a plurality of memory blocks. The method includes: periodically asserting a timing signal; asserting a refresh pending signal in each memory block when the asserted timing signal is received; within each memory block, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; within each memory block, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; within each memory block, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and forcing an idle cycle in all memory blocks if the refresh forcing signal is asserted.

7. 发明申请

WO2006083993A3 FABRICATION PROCESS FOR INCREASED CAPACITANCE IN AN EMBEDDED DRAM MEMORY 审中-公开
公开(公告)号：WO2006083993A3
公开(公告)日：2006-08-10
申请号：PCT/US2006/003622
申请日：2006-02-02
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , SINITSKY, Dennis , HSU, Fu-chieh
发明人： SINITSKY, Dennis , HSU, Fu-chieh
IPC分类号： H01L21/8242 , H01L27/108
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

8. 发明申请

WO2006057793A2 PREDICTIVE ERROR CORRECTION CODE GENERATION FACILITATING HIGH-SPEED BYTE-WRITE IN A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：预测误差校正代码生成在半导体存储器中实现高速字节写入
公开(公告)号：WO2006057793A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040086
申请日：2005-11-03
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu , TAM, Kit, Sang
发明人： LEUNG, Wingyu , TAM, Kit, Sang
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

9. 发明申请

WO2002061806A3 DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME 审中-公开
公开(公告)号：WO2002061806A3
公开(公告)日：2002-08-08
申请号：PCT/US2002/000846
申请日：2002-01-11
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： LEUNG, Wingyu , HSU, Fu-Chieh
IPC分类号： H01L21/8242
摘要： A memory system that includes a DRAM cell including an access transistor (3051) and a capacitor structure (3052) fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity (3025) in a shallow trench isolation region (3022), thereby exposing a sidewall portion of the substrate below the upper surface of the substrate. The capacitor structure is formed at least partially in the cavity, below the upper surface of the substrate. The capacitor structure extends over the sidewall portion of the substrate, thereby increasing the surface area of the capacitor structure, while minimizing the layout area of the capacitor structure. The memory system may include positive and/or negative boosted voltage generators coupled to a word line driver. The positive boosted voltage is less than one diode voltage drop greater than VDD. The negative boosted voltage is less than VSS by less than the absolute value of one diode voltage drop.

10. 发明申请

WO2002059901A1 SINGLE-PORT MULTI-BANK MEMORY SYSTEM HAVING READ AND WRITE BUFFERS AND METHOD OF OPERATING SAME 审中-公开
标题翻译：具有读取和写入缓冲器的单端口多单元存储器系统及其操作方法
公开(公告)号：WO2002059901A1
公开(公告)日：2002-08-01
申请号：PCT/US2002/000847
申请日：2002-01-11
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： LEUNG, Wingyu
IPC分类号： G11C11/406
CPC分类号： G11C11/005 , G06F12/0893 , G06F2212/3042 , G11C11/406 , G11C11/40618
摘要： A memory array that requires periodic refreshing is refreshed without explicit control signaling between the memory array and an external accessing client. External accesses and refresh operations are handled so that refresh operations do not interfere with external accesses under any conditions. This allows an SRAM-compatible device to be constructed from DRAM or 1-transistor cells. A single-port multi-bank refresh scheme reduces the number of collisions between refresh operations and external accesses. A read buffer buffers read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer buffers write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. The read and write buffers can both be constructed of DRAM cells.
摘要翻译：需要定期刷新的存储器阵列在存储器阵列和外部访问客户端之间没有显式控制信令的情况下被刷新。处理外部访问和刷新操作，以便刷新操作不会在任何情况下干扰外部访问。这允许SRAM兼容的器件由DRAM或1晶体管单元构成。单端口多行刷新方案可以减少刷新操作与外部访问之间的冲突次数。读取缓冲器缓冲读取数据，从而允许当连续读取访问长时间到达特定存储体的地址范围时执行刷新操作。写入缓冲器缓冲写入数据，从而允许在连续写入访问长时间到达特定存储体的地址范围时执行刷新操作。读和写缓冲器都可以由DRAM单元构成。

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