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1. 发明申请

WO2003042826A3 ERROR CORRECTING MEMORY AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2003042826A3
公开(公告)日：2003-05-22
申请号：PCT/GB2002/005123
申请日：2002-11-13
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC , FREEMAN, Jacqueline, Carol
发明人： LEUNG, Wingyu , HSU, Fu-Chieh
IPC分类号： G06F11/10
摘要： A memory device that uses error correction code (ECC) circuitry to improve the reliability of the memory device in view of single-bit errors caused by hard failure or soft error. A write buffer is used to post write data, so that ECC generation and memory write array operation can be carried out in parallel. As a result there is no penalty in write latency or memory cycle time due to ECC generation. A write-back buffer is used to post corrected ECC words during read operations, so that write-back of corrected ECC words does not need to take place during the same cycle that data is read. Instead, write-back operations are performed during idle cycles when no external memory access is requested, such that the write back operation does not impose a penalty on memory cycle time or affect memory access latency.

2. 发明申请

WO2002089140A2 METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING MULTIPLE CLOCK DIVISION 审中-公开
标题翻译：使用多个时钟段在DRAM设备中完全隐藏刷新操作的方法和装置
公开(公告)号：WO2002089140A2
公开(公告)日：2002-11-07
申请号：PCT/GB2002/001935
申请日：2002-04-26
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , FREEMAN, Jacqueline, Carol
发明人： LEUNG, Wingyu , SIM, Jae-Kwang
IPC分类号： G11C
CPC分类号： G11C11/005 , G11C7/22 , G11C11/406 , G11C11/40618
摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signalling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.
摘要翻译：一种用于处理需要周期性刷新操作的DRAM阵列或其它存储器阵列的刷新的方法和装置，使得刷新不需要显式控制信号，也不需要在存储器阵列与外部存取客户端之间的握手通信。该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。实现时钟分配方案，以允许在N个连续时钟周期内执行N个外部访问和一个刷新操作。

3. 发明申请

WO2007089558A2 METHOD TO INCREASE CHARGE RETENTION OF NON-VOLATILE MEMORY MANUFACTURED IN A SINGLE-GATE LOGIC PROCESS 审中-公开
标题翻译：增加在单门逻辑过程中制造的非易失性存储器的充电保持的方法
公开(公告)号：WO2007089558A2
公开(公告)日：2007-08-09
申请号：PCT/US2007/002118
申请日：2007-01-25
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： FANG, Gang-feng , SINITSKY, Dennis , LEUNG, Wingyu
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
摘要翻译：具有增加的电荷保持的非易失性存储单元在与使用单栅极常规逻辑工艺的逻辑器件相同的衬底上制造。在NVM单元的浮动栅极上形成硅化物阻挡电介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

4. 发明申请

WO2006057794A2 TRANSPARENT ERROR CORRECTING MEMORY THAT SUPPORTS PARTIAL-WORD WRITE 审中-公开
标题翻译：透明错误修正支持部分字写入的记忆
公开(公告)号：WO2006057794A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040087
申请日：2005-11-03
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu
发明人： LEUNG, Wingyu
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The read data word is corrected in response to the associated error correction bits, thereby creating a corrected data word. The corrected data word is merged with a write data word, thereby creating a merged write data word. Write error correction bits are generated in response to the merged write data word, and the merged write data word and write error correction bits are written to the memory array. The word line and the plurality of sense amplifiers remain enabled from the reading operation through the write operation, thereby speeding up the partial-word write operation.
摘要翻译：在存储器系统中执行高速部分字写入操作。首先，从存储器阵列读取包括数据字和相关联的纠错位的纠错码（ECC）字。在该读取操作期间，字线和多个读出放大器被使能。响应于相关联的纠错位来校正读取的数据字，由此创建校正的数据字。校正的数据字与写入数据字合并，从而创建合并的写入数据字。响应于合并的写入数据字产生写入纠错位，并且将合并的写入数据字和写入错误校正位写入存储器阵列。通过写入操作，字线和多个读出放大器从读取操作保持使能，从而加速部分字写入操作。

5. 发明申请

WO2002069344A3 METHOD AND APPARATUS FOR FORCING IDLE CYCLES TO ENABLE REFRESH OPERATIONS IN A SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：WO2002069344A3
公开(公告)日：2002-09-06
申请号：PCT/US2002/004439
申请日：2002-02-12
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： LEUNG, Wingyu
IPC分类号： G11C11/406
摘要： Method and apparatus for operating a memory system having a plurality of memory blocks. The method includes: periodically asserting a timing signal; asserting a refresh pending signal in each memory block when the asserted timing signal is received; within each memory block, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; within each memory block, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; within each memory block, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and forcing an idle cycle in all memory blocks if the refresh forcing signal is asserted.

6. 发明申请

WO2007002509A2 WORD LINE DRIVER FOR DRAM EMBEDDED IN A LOGIC PROCESS 审中-公开
标题翻译：用于嵌入逻辑过程的DRAM的字线驱动器
公开(公告)号：WO2007002509A2
公开(公告)日：2007-01-04
申请号：PCT/US2006/024653
申请日：2006-06-23
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu
发明人： LEUNG, Wingyu
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A word line driver provided for accessing a DRAM cell embedded in conventional logic process and includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and p-type substrate are coupled to ground. The polarities can be reversed in another embodiment.
摘要翻译：提供用于访问嵌入在常规逻辑处理中的DRAM单元的字线驱动器，并且包括耦合到单元电容器的p沟道存取晶体管。字线驱动器包括位于p阱中的n沟道晶体管，其中p阱位于深n阱中。深n阱位于p型衬底中。字线将n沟道晶体管的漏极耦合到p沟道存取晶体管的栅极。负升压电压对p沟道和n沟道晶体管的源极施加负升压电压。负升压电压小于接地，等于或大于p沟道存取晶体管的阈值电压。深n阱和p型衬底耦合到地面。在另一个实施例中，极性可以颠倒。

7. 发明申请

WO1997008705A1 METHOD AND STRUCTURE FOR CONTROLLING INTERNAL OPERATIONS OF A DRAM ARRAY 审中-公开
标题翻译：用于控制DRAM阵列内部操作的方法和结构
公开(公告)号：WO1997008705A1
公开(公告)日：1997-03-06
申请号：PCT/US1996013503
申请日：1996-08-29
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu
IPC分类号： G11C11/409
CPC分类号： G11C11/4076 , G11C7/22 , G11C11/4096
摘要： A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a rising edge of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before the falling edge of the clock signal occurs. The falling edge is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before the subsequent rising edge of the clock signal. The subsequent rising edge is then used to initiate the column address decoding operation of the DRAM array. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes.
摘要翻译：响应于行访问（RAS＃）信号和时钟信号的上升沿和下降沿来控制对DRAM阵列的访问定时的方法和结构。当接收到行存取信号并且检测到时钟信号的上升沿时，行地址解码和均衡电路的去激活被启动。在时钟信号的下降沿发生之前，行地址解码和均衡电路的去激活完成。然后，下降沿用于启动DRAM阵列的读出放大器的导通。读出放大器在时钟信号的后续上升沿之前导通。随后的上升沿用于启动DRAM阵列的列地址解码操作。包括测试模式，允许DRAM阵列异步运行以进行测试。

8. 发明申请

WO1996016371A1 METHOD AND STRUCTURE FOR UTILIZING A DRAM ARRAY AS SECOND LEVEL CACHE MEMORY 审中-公开
标题翻译：使用DRAM阵列作为第二级缓存存储器的方法和结构
公开(公告)号：WO1996016371A1
公开(公告)日：1996-05-30
申请号：PCT/US1995014552
申请日：1995-11-20
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu , HSU, Fu-Chieh
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0897
摘要： A method and structure for using a DRAM memory array (213) as a second level cache memory in a computer system (200). The computer system includes a central processing unit (CPU) (201), a first level SRAM cache memory (202), a CPU bus (204), and a second level cache memory (213) which includes a DRAM array (317) coupled to the CPU bus. In one embodiment, the DRAM array is operated at a higher frequency than the CPU bus clock signal. In another embodiment, a widened data path is provided to the DRAM array. Both embodiments effectively increase the data rate of the DRAM array, thereby providing additional time for precharging the DRAM array. As a result the precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统（200）中使用DRAM存储器阵列（213）作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU）（201），第一级SRAM高速缓冲存储器（202），CPU总线（204）和第二级高速缓冲存储器（213），其包括耦合到DRAM阵列到CPU总线。在一个实施例中，DRAM阵列以比CPU总线时钟信号更高的频率工作。在另一个实施例中，向DRAM阵列提供加宽的数据路径。两个实施例有效地增加了DRAM阵列的数据速率，从而为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

9. 发明申请

WO2006057793A2 PREDICTIVE ERROR CORRECTION CODE GENERATION FACILITATING HIGH-SPEED BYTE-WRITE IN A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：预测误差校正代码生成在半导体存储器中实现高速字节写入
公开(公告)号：WO2006057793A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040086
申请日：2005-11-03
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu , TAM, Kit, Sang
发明人： LEUNG, Wingyu , TAM, Kit, Sang
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

10. 发明申请

WO2002061806A3 DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME 审中-公开
公开(公告)号：WO2002061806A3
公开(公告)日：2002-08-08
申请号：PCT/US2002/000846
申请日：2002-01-11
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC.
发明人： LEUNG, Wingyu , HSU, Fu-Chieh
IPC分类号： H01L21/8242
摘要： A memory system that includes a DRAM cell including an access transistor (3051) and a capacitor structure (3052) fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity (3025) in a shallow trench isolation region (3022), thereby exposing a sidewall portion of the substrate below the upper surface of the substrate. The capacitor structure is formed at least partially in the cavity, below the upper surface of the substrate. The capacitor structure extends over the sidewall portion of the substrate, thereby increasing the surface area of the capacitor structure, while minimizing the layout area of the capacitor structure. The memory system may include positive and/or negative boosted voltage generators coupled to a word line driver. The positive boosted voltage is less than one diode voltage drop greater than VDD. The negative boosted voltage is less than VSS by less than the absolute value of one diode voltage drop.

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