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1. 发明专利

JP2011023700A Field effect transistor and method of manufacturing the same 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：JP2011023700A
公开(公告)日：2011-02-03
申请号：JP2010056327
申请日：2010-03-12
申请人： Chartered Semiconductor Manufacturing Ltd , Toshiba Corp , チャータード・セミコンダクター・マニュファクチャリング・リミテッド , 株式会社東芝
发明人： OTA HIROYUKI , SIH VINCENT
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/165 , H01L21/26586 , H01L21/28052 , H01L21/28255 , H01L29/1054 , H01L29/1083 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor having high quality characteristics, and to provide a method of manufacturing the same.
SOLUTION: The field effect transistor includes a semiconductor substrate 102 which contains a source/drain region 114 between element isolation regions 106 and a pocket region 116, a silicon germanium layer 112 which resides in a trench 110 at an upper surface of the semiconductor substrate 102 between the element isolation regions 106 and has a bottom surface and an upper surface with a (100) plane and side faces with two or more planes, a gate structure on the silicon germanium layer 112 containing a gate insulating layer 120, a gate electrode 122 and a side spacer 128, and a metal silicide 124 on upper parts of the silicon germanium layer 112 and semiconductor substrate 102 which are not covered with the gate structure, wherein the silicon germanium layer 112 has not any side face under the gate structure in the channel length direction.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有高质量特性的场效应晶体管，并提供其制造方法。解决方案：场效应晶体管包括半导体衬底102，其包含元件隔离区域106和穴状区域116之间的源极/漏极区域114，位于沟槽110的上表面的硅锗层112 元件隔离区域106之间的半导体衬底102具有底表面和具有（100）面的上表面，并且具有两个或多个平面的侧面，硅锗层112上的栅极结构包含栅极绝缘层120，栅电极122和侧隔板128，以及未被栅极结构覆盖的硅锗层112和半导体衬底102的上部的金属硅化物124，其中硅锗层112在栅极下方没有任何侧面结构在通道长度方向上。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2013179323A Method of manufacturing semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：JP2013179323A
公开(公告)日：2013-09-09
申请号：JP2013085597
申请日：2013-04-16
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd. , Chartered Semiconductor Manufacturing Ltd , チャータード・セミコンダクター・マニュファクチャリング・リミテッド , Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation , Infineon Technologies North America Corp , インフィネオンテクノロジーズノースアメリカコーポレイション
发明人： PARK SANG-JINE , HENRY RICHARD O , TAN YONG SIANG , KWON OH SUNG , KWON OH-JUNG
IPC分类号： H01L21/336 , H01L21/308 , H01L21/76 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66636 , H01L21/31111 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device which allow for stabilized etching.SOLUTION: The method of manufacturing a semiconductor integrated circuit device includes a step for forming a field effect transistor including a gate electrode 120, sacrifice nitride film spacer 150 formed on both sidewalls of the gate electrode, and a source/drain region 160 self-aligned with the sacrifice nitride film spacer, a step for selectively removing the sacrifice nitride film spacer by hydrofluoric acid having a selective ratio of the nitride film for the oxide film of larger than 1, and a step for forming a stress film, which derives tensile or compressive stress in the channel region of the field effect transistor, on both sidewalls of the gate electrode.
摘要翻译：要解决的问题：提供一种制造允许稳定蚀刻的半导体集成电路器件的方法。解决方案：半导体集成电路器件的制造方法包括用于形成包括栅电极120的场效应晶体管的步骤，牺牲氮化物形成在栅电极的两个侧壁上的膜间隔物150以及与牺牲氮化物膜间隔物自对准的源极/漏极区域160，用氮化物膜选择性比例的氢氟酸选择性去除牺牲氮化物膜间隔物的步骤对于大于1的氧化膜，以及在栅电极的两个侧壁上形成在场效应晶体管的沟道区域中产生拉伸或压应力的应力膜的步骤。

3. 发明授权

EP1304730B1 Manufacturing method of a nanocrystal flash memory 有权
标题翻译：一种制造纳米晶体快闪存储器装置的方法
公开(公告)号：EP1304730B1
公开(公告)日：2011-01-12
申请号：EP02256661.6
申请日：2002-09-25
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Choi, Wee Kiong , Chim, Wai Kin , NG, Vivian , Chan, Lap
IPC分类号： H01L21/28
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42332

4. 发明公开

EP1227521A3 A method to form a transistor with multiple threshold voltages using a combination of different work function gate materials 审中-公开
标题翻译：一种用于提供与具有不同功函数的材料制成的栅极几个阈值晶体管的制备方法
公开(公告)号：EP1227521A3
公开(公告)日：2007-01-24
申请号：EP02368009.3
申请日：2002-01-24
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Chan, Lap , Quek, Elgin , Sundaresan, Ravi , Pan, Yang , Lee, James Yong Meng , Leung, Ying Keung , Pradeep, Yelehanka Ramachandramurthy , Zheng, Jia Zhen
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/82345 , H01L21/28105 , H01L29/495 , H01L29/4966 , H01L29/4983 , H01L29/66583
摘要： A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF1 material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF2 material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.

5. 发明公开

EP1220317A3 ESD protection structure 审中-公开
标题翻译： ESD保护令
公开(公告)号：EP1220317A3
公开(公告)日：2006-10-11
申请号：EP01124898.6
申请日：2001-10-18
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Cai, Jun c/o Fairchild Semiconductor , Hua, Guang Ping , Song, Jun, Block 210, No. 7-196 , Lo, Keng Foo
IPC分类号： H01L27/02
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure [10] is provided for ESD protection in an integrated circuit device. A semiconductor substrate [12] has source and drain diffusion regions [14,16] and respective source and drain wells [18,20] under the source and drain diffusion regions [14,16]. A shallow trench isolation [28] formed over the semiconductor substrate [12] and into the semiconductor substrate [12] separates the source and drain diffusion regions [14,16] and a portion of the source and drain wells [18,20]. Source and drain contact structures [42,44] respectively formed on the shallow trench isolation [28] over the source and drain diffusion regions [14,16] and extend through the shallow trench isolation [28] to contact the source and drain diffusion regions [14,16]. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells [18,20] to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

6. 发明公开

EP1321972A3 Trimming process for a structure of photoresist and organic antireflective layer 审中-公开
标题翻译：修整方法用于光致抗蚀剂和有机防反射层的图案
公开(公告)号：EP1321972A3
公开(公告)日：2005-02-16
申请号：EP02020253.7
申请日：2002-09-10
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Ramachandramurthy, Pradeep Yelehanka , Loong, Loh Wei , Yu, Jie , Qing, Chen Tong
IPC分类号： H01L21/027 , H01L21/311
CPC分类号： H01L21/0276 , G03F7/40 , H01L21/31138
摘要： A method for etching an organic bottom antireflective coating (OBARC) and a photoresist material in a single etching process. The method comprises the steps of etching the OBARC and trimming the photoresist material at the same time in an etching environment using a substantially isotropic etching operation. The etching environment including an etching chamber with a top electrode and a bottom electrode wherein a mixture of abrasive gases can flow therethrough. Using an endpoint detection test to determine when an exposed portion of OBARC has been removed, the exposed portion of OBARC being an area of OBARC without photoresist protection and exposed to the etching environment. Applying an over-etch step to trim the photoresist to a desired dimension where the time of the over-etch step being based on the percentage of an endpoint time and the process condition of the over-etch step being same as that of the endpoint step.

7. 发明公开

EP1324375A3 Via/line inductor on semiconductor material 审中-公开
标题翻译：电感器上的半导体材料
公开(公告)号：EP1324375A3
公开(公告)日：2004-09-01
申请号：EP02257729.0
申请日：2002-11-07
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Jiong, Zhang , Wang, Yi Min , Chu, Shao-fu Sanford
IPC分类号： H01L21/02 , H01L27/08
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902
摘要： A spiral inductor [122], and manufacturing method therefore, is provided including a substrate [112] and an inductor dielectric layer [114] over the substrate [112] having a spiral opening provided therein. A spiral inductor [122] is in the spiral opening with the spiral inductor [122] including a plurality of parallel spiral vias [144] [148] connected together at center proximate and center distal ends of the spiral inductor [122].

8. 发明公开

EP1435656A2 Method of manufacturing a dual damascene interconnect 审中-公开
标题翻译： Herstellung einer Doppel-Damaszener-Verbindungsstruktur
公开(公告)号：EP1435656A2
公开(公告)日：2004-07-07
申请号：EP03025373.6
申请日：2003-11-04
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Wuping, Liu , Tan, Juan Boon , Zhang, Bei Chao , Cuthbertson, Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An integrated circuit (100,200) manufacturing method (300) includes providing a base (102,202), forming thereon a first conductor (104,204), forming thereon a first barrier layer (106,206), forming thereon a first dielectric layer (108,208), and forming a masking layer (116). The method (300) further including forming a first via opening (120,218) in the masking layer (116), forming a first trench opening (124,226) in the masking layer (116), and simultaneously forming a second via opening (130,220) in a layer (114,112) under the masking layer (116), and forming a second trench (132,230) opening through the masking layer (116,214) and in the layer (114,112) under the masking layer (116,214) and simultaneously forming a third via opening (134,228) in another layer (110,108) under the masking layer (116). The method (300) further including removing the first barrier layer (106,206) using the third via opening (134,228) and the masking layer (116,214) to form a trench (132,230) and a via (134,232), and filling the trench (132,230) and the via (134,232) with a conductor to form a trench and via conductor (136,234) in contact with the first conductor (104,204).
摘要翻译：集成电路（100,200）制造方法（300）包括提供基座（102,202），在其上形成有第一导体（104,204），在其上形成第一阻挡层（106,206），在其上形成第一d

9. 发明公开

EP1396875A2 3-D spiral stacked inductor on semiconductor material 失效
标题翻译： 3-DspiralförmigeSpule auf einem Halbleitermaterial
公开(公告)号：EP1396875A2
公开(公告)日：2004-03-10
申请号：EP03019916.0
申请日：2003-09-02
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Sia, Choon-Beng , Yeo, Kiat Seng , Chu, Shao-fu Sandford , NG, Cheng Yeow , Chew, Kok Wai , Goh, Wang Ling
IPC分类号： H01L21/02
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902 , Y10T29/4906 , Y10T29/49073 , Y10T29/49165
摘要： A 3-D spiral stacked inductor is provided having a substrate (112) with a plurality of turns (124, 126, 128) in a plurality of levels (150', 150", 150"') wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions (130, 134) are respectively connected to an inner turn and an outermost turn, and a dielectric material (116, 121) contains the first and second connecting portions (130, 134) and the plurality of turns (124, 126, 128) over the substrate (112).
摘要翻译：提供了具有多个电平（150'，150“，150”'）的多个匝数（124,126,128）的衬底（112）的3-D螺旋堆叠电感器，其中电平数量从内部转向电感器的外圈。第一和第二连接部分（130,134）分别连接到内匝和最外匝，并且介电材料（116,121）包含第一和第二连接部分（130,134）和多匝（124），126,128）。

10. 发明公开

EP1324375A2 Via/line inductor on semiconductor material 审中-公开
标题翻译： Induktivitätauf einem Halbleitermaterial
公开(公告)号：EP1324375A2
公开(公告)日：2003-07-02
申请号：EP02257729.0
申请日：2002-11-07
申请人： Chartered Semiconductor Manufacturing ,Ltd.
发明人： Jiong, Zhang , Wang, Yi Min , Chu, Shao-fu Sanford
IPC分类号： H01L21/02 , H01L27/08
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902
摘要： A spiral inductor [122], and manufacturing method therefore, is provided including a substrate [112] and an inductor dielectric layer [114] over the substrate [112] having a spiral opening provided therein. A spiral inductor [122] is in the spiral opening with the spiral inductor [122] including a plurality of parallel spiral vias [144] [148] connected together at center proximate and center distal ends of the spiral inductor [122].
摘要翻译：因此，提供螺旋电感器Ä122Ü及其制造方法，其包括衬底Ä112ü和电感器电介质层Ä114Ü在衬底上具有设置在其中的螺旋形开口。螺旋电感器Ä122Ü处于螺旋形开口中，螺旋电感器包括在螺旋电感器Ä122Ü的中心邻近和中心远端处连接在一起的多个平行螺旋通孔Ä144ÜÄ148Ü。

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