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1. 发明公开

EP1220317A3 ESD protection structure 审中-公开
标题翻译： ESD保护令
公开(公告)号：EP1220317A3
公开(公告)日：2006-10-11
申请号：EP01124898.6
申请日：2001-10-18
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Cai, Jun c/o Fairchild Semiconductor , Hua, Guang Ping , Song, Jun, Block 210, No. 7-196 , Lo, Keng Foo
IPC分类号： H01L27/02
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure [10] is provided for ESD protection in an integrated circuit device. A semiconductor substrate [12] has source and drain diffusion regions [14,16] and respective source and drain wells [18,20] under the source and drain diffusion regions [14,16]. A shallow trench isolation [28] formed over the semiconductor substrate [12] and into the semiconductor substrate [12] separates the source and drain diffusion regions [14,16] and a portion of the source and drain wells [18,20]. Source and drain contact structures [42,44] respectively formed on the shallow trench isolation [28] over the source and drain diffusion regions [14,16] and extend through the shallow trench isolation [28] to contact the source and drain diffusion regions [14,16]. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells [18,20] to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

2. 发明公开

EP1220317A2 ESD protection structure 审中-公开
标题翻译： ESD-Schutzanordnung
公开(公告)号：EP1220317A2
公开(公告)日：2002-07-03
申请号：EP01124898.6
申请日：2001-10-18
申请人： Chartered Semiconductor Manufacturing ,Ltd.
发明人： Cai, Jun , Hua, Guang Ping , Song, Jun , Lo, Keng Foo
IPC分类号： H01L27/02
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure [10] is provided for ESD protection in an integrated circuit device. A semiconductor substrate [12] has source and drain diffusion regions [14,16] and respective source and drain wells [18,20] under the source and drain diffusion regions [14,16]. A shallow trench isolation [28] formed over the semiconductor substrate [12] and into the semiconductor substrate [12] separates the source and drain diffusion regions [14,16] and a portion of the source and drain wells [18,20]. Source and drain contact structures [42,44] respectively formed on the shallow trench isolation [28] over the source and drain diffusion regions [14,16] and extend through the shallow trench isolation [28] to contact the source and drain diffusion regions [14,16]. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells [18,20] to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.
摘要翻译：在集成电路器件中提供用于ESD保护的晶体管结构[10]。半导体衬底[12]在源极和漏极扩散区[14,16]下面具有源极和漏极扩散区[14,16]以及相应的源极和漏极[18,20]。形成在半导体衬底[12]上并进入半导体衬底[12]的浅沟槽隔离[28]分离源极和漏极扩散区域[14,16]以及源极和漏极阱[18,20]的一部分。分别在源极和漏极扩散区[14,16]上的浅沟槽隔离[28]上形成源极和漏极接触结构[42,44]，并延伸穿过浅沟槽隔离[28]，以接触源极和漏极扩散区 [14,16]。通过接触开口进入离子注入到源阱和漏极井[18,20]的底部，以控制器件触发电压并将放电电流定位远离表面，从而显着提高器件ESD性能。

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