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1. 发明公开

EP1435656A2 Method of manufacturing a dual damascene interconnect 审中-公开
标题翻译： Herstellung einer Doppel-Damaszener-Verbindungsstruktur
公开(公告)号：EP1435656A2
公开(公告)日：2004-07-07
申请号：EP03025373.6
申请日：2003-11-04
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Wuping, Liu , Tan, Juan Boon , Zhang, Bei Chao , Cuthbertson, Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An integrated circuit (100,200) manufacturing method (300) includes providing a base (102,202), forming thereon a first conductor (104,204), forming thereon a first barrier layer (106,206), forming thereon a first dielectric layer (108,208), and forming a masking layer (116). The method (300) further including forming a first via opening (120,218) in the masking layer (116), forming a first trench opening (124,226) in the masking layer (116), and simultaneously forming a second via opening (130,220) in a layer (114,112) under the masking layer (116), and forming a second trench (132,230) opening through the masking layer (116,214) and in the layer (114,112) under the masking layer (116,214) and simultaneously forming a third via opening (134,228) in another layer (110,108) under the masking layer (116). The method (300) further including removing the first barrier layer (106,206) using the third via opening (134,228) and the masking layer (116,214) to form a trench (132,230) and a via (134,232), and filling the trench (132,230) and the via (134,232) with a conductor to form a trench and via conductor (136,234) in contact with the first conductor (104,204).
摘要翻译：集成电路（100,200）制造方法（300）包括提供基座（102,202），在其上形成有第一导体（104,204），在其上形成第一阻挡层（106,206），在其上形成第一d

2. 发明公开

EP1435656A3 Method of manufacturing a dual damascene interconnect 审中-公开
标题翻译：双镶嵌互连结构的制备
公开(公告)号：EP1435656A3
公开(公告)日：2006-04-12
申请号：EP03025373.6
申请日：2003-11-04
申请人： Chartered Semiconductor Manufacturing Ltd.
发明人： Wuping, Liu , Tan, Juan Boon , Zhang, Bei Chao , Cuthbertson, Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An integrated circuit (100,200) manufacturing method (300) includes providing a base (102,202), forming thereon a first conductor (104,204), forming thereon a first barrier layer (106,206), forming thereon a first dielectric layer (108,208), and forming a masking layer (116). The method (300) further including forming a first via opening (120,218) in the masking layer (116), forming a first trench opening (124,226) in the masking layer (116), and simultaneously forming a second via opening (130,220) in a layer (114,112) under the masking layer (116), and forming a second trench (132,230) opening through the masking layer (116,214) and in the layer (114,112) under the masking layer (116,214) and simultaneously forming a third via opening (134,228) in another layer (110,108) under the masking layer (116). The method (300) further including removing the first barrier layer (106,206) using the third via opening (134,228) and the masking layer (116,214) to form a trench (132,230) and a via (134,232), and filling the trench (132,230) and the via (134,232) with a conductor to form a trench and via conductor (136,234) in contact with the first conductor (104,204).

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