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1. 发明专利

JPH023986A MANUFACTURE OF HIGH DENSITY DIVIDED GATE NONVOLATILE MEMORY CELL 失效
公开(公告)号：JPH023986A
公开(公告)日：1990-01-09
申请号：JP1421989
申请日：1989-01-25
申请人： CATALYST SEMICONDUCTOR INC
发明人： SUTEIIBU KEI SHIA , PURITOPARU SHIN MAHAARU , UEIIREN SHII
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE: To miniaturize a memory cell by forming a control gate above a floating gate, overlapping it with a part of a source region, executing etching and self-alignment above a drain area and the source region and shortening channel length. CONSTITUTION: An oxide layer 11 is thermally grown on a substrate 10, a polysilicon layer 12 is pattern-formed on the layer to demarcate the floating gate 12. Then, a gate oxide 14 is thermally grown on the floating gate 12 and a polysilicon layer 16 is formed. Then, the mask material 18 of silicon oxide and the like is deposited and formed on the layer. The control gate is etched from the polysilicon layer 16 to the gate oxide 14. One etched side part is provided above the drain region and the other etched side part above the source region. Then, an etching mask for self-alignment 22 is deposited on a part of the control gate 16 and the source region is protected from etching acid. Thus, channel length is shortened and the memory cell can be miniaturized.

2. 发明专利

JPH0642552B2 失效
公开(公告)号：JPH0642552B2
公开(公告)日：1994-06-01
申请号：JP1421989
申请日：1989-01-25
申请人： CATALYST SEMICONDUCTOR INC
发明人： SUTEIIBU KEI SHIA , PURITOPARU SHIN MAHAARU , UEIIREN SHII
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792

3. 发明申请

WO2008103835A3 FRACTIONAL CHARGE PUMP FOR STEP-DOWN DC-DC CONVERTER 审中-公开
标题翻译：用于降压DC-DC转换器的分体充电泵
公开(公告)号：WO2008103835A3
公开(公告)日：2008-10-16
申请号：PCT/US2008054596
申请日：2008-02-21
申请人： CATALYST SEMICONDUCTOR INC , GEORGESCU SORIN S , RUSSELL ANTHONY G , BARTHOLOMEUEZ CHRIS
发明人： GEORGESCU SORIN S , RUSSELL ANTHONY G , BARTHOLOMEUEZ CHRIS
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a multiplication factor of 2/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the output terminal is connected to the common node of the first and second capacitors. In a third mode, the voltage potential across the second capacitor is subtracted from the sum of the input voltage and the voltage potential across the first capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 2/3x voltage multiplication. This relatively low multiplication factor can be beneficial in applications requiring 2.5V and 1.8V supplies for integrated circuits, particularly where the input voltage is provided by a lithium battery.
摘要翻译：电荷泵通过使用三相工作模式提供2/3的倍增系数。在第一模式中，第一和第二电容器从输入电压充电，而第三电容器基于第三电容器中存储的电荷来驱动输出电压。在第二模式中，输出端子连接到第一和第二电容器的公共节点。在第三模式中，从第一电容器两端的输入电压和电压电平之和减去第二电容器两端的电压电位，以产生输出电压。以这种方式操作，第一，第二和第三电容器将提供期望的2 / 3x电压倍增。这种相对较低的乘法因子对于集成电路需要2.5V和1.8V电源的应用可能是有益的，特别是在输入电压由锂电池提供的情况下。

4. 发明申请

WO2008030796B1 SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY 审中-公开
标题翻译：可拆卸电可擦除和可编程存储器
公开(公告)号：WO2008030796B1
公开(公告)日：2008-06-12
申请号：PCT/US2007077514
申请日：2007-09-04
申请人： CATALYST SEMICONDUCTOR INC , GEORGESCU SORIN S , COSMIN PETER , SMARANDOIU GEORGE
发明人： GEORGESCU SORIN S , COSMIN PETER , SMARANDOIU GEORGE
IPC分类号： H01L29/788
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储器晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和向下延伸穿过第一阱区域以接触第二阱区域的漏极区域。第一，第二和第三半导体区域和第二阱区域具有第一导电类型，并且第一阱区域具有与第一导电类型相反的第二导电类型。

5. 发明申请

WO2008028129A2 NON-VOLATILE MEMORY CELL IN STANDARD CMOS PROCESS 审中-公开
标题翻译：标准CMOS工艺中的非易失性存储器单元
公开(公告)号：WO2008028129A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/077386
申请日：2007-08-31
申请人： CATALYST SEMICONDUCTOR, INC. , EFTIMIE, Sabin A. , POENARU, Ilie Marian I. , GEORGESCU, Sorin S.
发明人： EFTIMIE, Sabin A. , POENARU, Ilie Marian I. , GEORGESCU, Sorin S.
IPC分类号： G11C11/24
CPC分类号： G11C16/0441
摘要： Non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
摘要翻译：利用常规CMOS工艺制造的非易失性存储器单元包括具有与写入PMOS电容器和擦除PMOS电容器共享浮置栅极的NMOS晶体管的触发器电路。擦除功能通过在擦除PMOS电容器中引发Fowler-Nordheim隧穿来实现，从而在浮动栅极上提供正电荷。写入功能通过诱导通过NMOS晶体管的福勒 - 诺德海姆隧穿实现，由此在浮置栅极上提供负电荷。写入PMOS电容在擦除和写入操作期间提供偏置电压。在读操作之前，触发器电路被复位。如果浮动栅极存储正电荷，则NMOS晶体管导通，从而切换触发器电路的状态。如果浮动栅极存储负电荷，则NMOS晶体管关断，从而使触发器电路处于复位状态。

6. 发明申请

WO2007097933A3 PRECISION NON-VOLATILE CMOS REFERENCE CIRCUIT 审中-公开
标题翻译：精密非易失性CMOS参考电路
公开(公告)号：WO2007097933A3
公开(公告)日：2008-07-31
申请号：PCT/US2007003610
申请日：2007-02-09
申请人： CATALYST SEMICONDUCTOR INC
发明人： NEGUT ALINA I , GEORGESCU SORIN S , EFTIMIE SABIN
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C5/147
摘要： A voltage reference circuit (100) provides a reference voltage that can be precisely programmed The threshold voltage of a first non-volatile memory CNVM) transistor (10) is programmed while coupled in parallel with a second NVM transistor (11) During programming, one or more capacitors (Cl) are connected between the floating gate (40) of the first NVM transistor (10) and ground, and one or more capacitors (C2B) are connected between the floating gate (41) of the second NVM transistor (11) and ground. The first and second NVM transistors (10, 11) are then coupled to a differential amplifier (35), which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.
摘要翻译：电压参考电路（100）提供可精确编程的参考电压。第一非易失性存储器CNVM）晶体管（10）的阈值电压被编程，并与第二NVM晶体管（11）并联编程。在编程期间，一个或更多个电容器（C1）连接在第一NVM晶体管（10）的浮置栅极（40）和地之间，并且一个或多个电容器（C2B）连接在第二NVM晶体管（11）的浮置栅极（41））和地面。第一和第二NVM晶体管（10,11）然后被耦合到差分放大器（35），该差分放大器用于响应于第一NVM晶体管的编程阈值电压而产生单端参考电压。双极晶体管被选择性地切换在各种电容器和地之间，从而提供对电压参考电路的温度系数的精确调节。

7. 发明申请

WO2008028129A3 NON-VOLATILE MEMORY CELL IN STANDARD CMOS PROCESS 审中-公开
标题翻译：标准CMOS工艺中的非易失性存储单元
公开(公告)号：WO2008028129A3
公开(公告)日：2008-07-10
申请号：PCT/US2007077386
申请日：2007-08-31
申请人： CATALYST SEMICONDUCTOR INC , EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
发明人： EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
IPC分类号： G11C11/24
CPC分类号： G11C16/0441
摘要： Non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
摘要翻译：使用常规CMOS工艺制造的非易失性存储单元，包括具有与写入PMOS电容器共享浮置栅极的NMOS晶体管和擦除PMOS电容器的触发器电路。通过将Fowler-Nordheim隧道穿过擦除PMOS电容器来实现擦除功能，从而在浮动栅极上提供正电荷。通过引入通过NMOS晶体管的Fowler-Nordheim隧道实现写入功能，从而在浮动栅极上提供负电荷。写入PMOS电容器在擦除和写入操作期间提供偏置电压。在读操作之前，触发器电路被复位。如果浮置栅极存储正电荷，则NMOS晶体管导通，从而切换触发器电路的状态。如果浮动栅极存储负电荷，则NMOS晶体管截止，从而使触发器电路处于复位状态。

8. 发明申请

WO2007106135A2 PRECISION NON-VOLATILE CMOS REFERENCE CIRCUIT 审中-公开
标题翻译：精密非易失性CMOS参考电路
公开(公告)号：WO2007106135A2
公开(公告)日：2007-09-20
申请号：PCT/US2006/036954
申请日：2006-09-21
申请人： CATALYST SEMICONDUCTOR, INC.
发明人： POENARU, Illie, Marian, I. , EFTIMIE, Sabin, A. , GEORGESCU, Sorin, S.
IPC分类号： G11C5/14
CPC分类号： G11C16/30
摘要： A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.
摘要翻译：电压参考电路提供可精确编程的参考电压。第一非易失性存储器（NVM）晶体管的阈值电压被编程，并与参考NVM晶体管并联。在编程期间，参考NVM晶体管具有通过第一组电容器耦合到地的浮置栅极，并通过第二组电容器耦合到参考电压。第一NVM晶体管的编程阈值电压取决于第一组和第二组电容器。然后第一和参考NVM晶体管并联耦合，并且差分放大器用于响应于第一NVM晶体管的编程阈值电压而产生单端参考电压。电容器可以在第一组和第二组之间传输，从而提供单端参考电压的精确调整。

9. 发明申请

WO2007053247A2 LED BIAS CURRENT CONTROL USING ADAPTIVE FRACTIONAL CHARGE PUMP 审中-公开
公开(公告)号：WO2007053247A2
公开(公告)日：2007-05-10
申请号：PCT/US2006036955
申请日：2006-09-21
申请人： CATALYST SEMICONDUCTOR INC
发明人： GEORGESCU SORIN S , RUSSELL ANTHONY G , BARTHOLOMEUSZ CHRIS B
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H05B33/0815 , Y02B20/347
摘要： A charge pump provides a multiplication factor of 4/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the voltage potential across the first capacitor is added to the input voltage to generate the output voltage. In a third mode, the voltage potential across the first capacitor is subtracted from the sum of the input voltage and the voltage potential across the second capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 4/3x voltage multiplication. This relatively low multiplication factor can be beneficial in applications such as white LED driver circuits, particularly where the input voltage is provided by a battery.

10. 发明申请

WO2008070578A3 METHOD FOR REDUCING CHARGE LOSS IN ANALOG FLOATING GATE CELL 审中-公开
标题翻译：降低模拟浮动栅极单元中的电荷损失的方法
公开(公告)号：WO2008070578A3
公开(公告)日：2008-08-28
申请号：PCT/US2007086175
申请日：2007-11-30
申请人： CATALYST SEMICONDUCTOR INC , SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
发明人： SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
摘要翻译：电压参考电路响应于第一非易失性存储器（NVM）晶体管的编程的阈值电压来提供参考电压。第一NVM晶体管的阈值电压通过将编程电压施加到与第一NVM晶体管共享浮置栅极的隧穿电容器的公共连接的源极/漏极区域来编程。在电压参考电路的正常操作期间，隧穿电容器的源极/漏极区域连接到第二NVM晶体管，该第二NVM晶体管具有与第一NVM晶体管的浮置栅极相同的电和热特性。结果，来自第一NVM晶体管的浮置栅极的电荷损失有利地被最小化。

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