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1. 发明申请

WO2008070578A3 METHOD FOR REDUCING CHARGE LOSS IN ANALOG FLOATING GATE CELL 审中-公开
标题翻译：降低模拟浮动栅极单元中的电荷损失的方法
公开(公告)号：WO2008070578A3
公开(公告)日：2008-08-28
申请号：PCT/US2007086175
申请日：2007-11-30
申请人： CATALYST SEMICONDUCTOR INC , SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
发明人： SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
摘要翻译：电压参考电路响应于第一非易失性存储器（NVM）晶体管的编程的阈值电压来提供参考电压。第一NVM晶体管的阈值电压通过将编程电压施加到与第一NVM晶体管共享浮置栅极的隧穿电容器的公共连接的源极/漏极区域来编程。在电压参考电路的正常操作期间，隧穿电容器的源极/漏极区域连接到第二NVM晶体管，该第二NVM晶体管具有与第一NVM晶体管的浮置栅极相同的电和热特性。结果，来自第一NVM晶体管的浮置栅极的电荷损失有利地被最小化。

2. 发明申请

WO2008028129A3 NON-VOLATILE MEMORY CELL IN STANDARD CMOS PROCESS 审中-公开
标题翻译：标准CMOS工艺中的非易失性存储单元
公开(公告)号：WO2008028129A3
公开(公告)日：2008-07-10
申请号：PCT/US2007077386
申请日：2007-08-31
申请人： CATALYST SEMICONDUCTOR INC , EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
发明人： EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
IPC分类号： G11C11/24
CPC分类号： G11C16/0441
摘要： Non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
摘要翻译：使用常规CMOS工艺制造的非易失性存储单元，包括具有与写入PMOS电容器共享浮置栅极的NMOS晶体管和擦除PMOS电容器的触发器电路。通过将Fowler-Nordheim隧道穿过擦除PMOS电容器来实现擦除功能，从而在浮动栅极上提供正电荷。通过引入通过NMOS晶体管的Fowler-Nordheim隧道实现写入功能，从而在浮动栅极上提供负电荷。写入PMOS电容器在擦除和写入操作期间提供偏置电压。在读操作之前，触发器电路被复位。如果浮置栅极存储正电荷，则NMOS晶体管导通，从而切换触发器电路的状态。如果浮动栅极存储负电荷，则NMOS晶体管截止，从而使触发器电路处于复位状态。

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