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1. 发明申请

WO2008028129A3 NON-VOLATILE MEMORY CELL IN STANDARD CMOS PROCESS 审中-公开
标题翻译：标准CMOS工艺中的非易失性存储单元
公开(公告)号：WO2008028129A3
公开(公告)日：2008-07-10
申请号：PCT/US2007077386
申请日：2007-08-31
申请人： CATALYST SEMICONDUCTOR INC , EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
发明人： EFTIMIE SABIN A , POENARU ILIE MARIAN I , GEORGESCU SORIN S
IPC分类号： G11C11/24
CPC分类号： G11C16/0441
摘要： Non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
摘要翻译：使用常规CMOS工艺制造的非易失性存储单元，包括具有与写入PMOS电容器共享浮置栅极的NMOS晶体管和擦除PMOS电容器的触发器电路。通过将Fowler-Nordheim隧道穿过擦除PMOS电容器来实现擦除功能，从而在浮动栅极上提供正电荷。通过引入通过NMOS晶体管的Fowler-Nordheim隧道实现写入功能，从而在浮动栅极上提供负电荷。写入PMOS电容器在擦除和写入操作期间提供偏置电压。在读操作之前，触发器电路被复位。如果浮置栅极存储正电荷，则NMOS晶体管导通，从而切换触发器电路的状态。如果浮动栅极存储负电荷，则NMOS晶体管截止，从而使触发器电路处于复位状态。

2. 发明申请

WO2008103838A1 PROGRAMMABLE FRACTIONAL CHARGE PUMP FOR DC-DC CONVERTER 审中-公开
标题翻译：用于DC-DC转换器的可编程充电电荷泵
公开(公告)号：WO2008103838A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/054601
申请日：2008-02-21
申请人： CATALYST SEMICONDUCTOR, INC. , GEORGESCU, Sorin S. , RUSSELL, Anthony G. , BARTHOLOMEUEZ, Chris
发明人： GEORGESCU, Sorin S. , RUSSELL, Anthony G. , BARTHOLOMEUEZ, Chris
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generated by connecting a second plurality of M capacitors in a second plurality of M+1 configurations. The first plurality of N capacitors and the second plurality of M capacitors have one or more capacitors in common. The integers M and N may be equal, although this is not required. The first plurality of configurations is different than the second plurality of configurations, thereby providing different multiplication factors for the first and second pluralities of configurations. In one embodiment, the first plurality of (N+1) configurations results in an output voltage of about 3/4x an input voltage.
摘要翻译：电荷泵提供用于产生输出电压的可编程乘法因子。可以通过以第一多个（N + 1）配置连接第一多个N个电容器来产生第一输出电压。可以通过以第二多个M + 1配置的第二多个M个电容器连接来产生第二输出电压。第一多个N个电容器和第二个多个M个电容器具有共同的一个或多个电容器。整数M和N可以相等，尽管这不是必需的。第一多个配置与第二多个配置不同，从而为第一和第二多个配置提供不同的乘法因子。在一个实施例中，第一多个（N + 1）配置导致输入电压约为3 / 4x的输出电压。

3. 发明申请

WO2008103835A2 FRACTIONAL CHARGE PUMP FOR STEP-DOWN DC-DC CONVERTER 审中-公开
标题翻译：降压DC-DC转换器的分数电荷泵
公开(公告)号：WO2008103835A2
公开(公告)日：2008-08-28
申请号：PCT/US2008/054596
申请日：2008-02-21
申请人： CATALYST SEMICONDUCTOR, INC. , GEORGESCU, Sorin S. , RUSSELL, Anthony G. , BARTHOLOMEUEZ, Chris
发明人： GEORGESCU, Sorin S. , RUSSELL, Anthony G. , BARTHOLOMEUEZ, Chris
IPC分类号： H01L29/94
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a multiplication factor of 2/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the output terminal is connected to the common node of the first and second capacitors. In a third mode, the voltage potential across the second capacitor is subtracted from the sum of the input voltage and the voltage potential across the first capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 2/3x voltage multiplication. This relatively low multiplication factor can be beneficial in applications requiring 2.5V and 1.8V supplies for integrated circuits, particularly where the input voltage is provided by a lithium battery.
摘要翻译：
电荷泵通过使用三相操作模式提供倍增因子2/3。在第一模式中，第一和第二电容器从输入电压充电，而第三电容器基于第三电容器中存储的电荷驱动输出电压。在第二模式中，输出端连接到第一和第二电容器的公共节点。在第三模式中，从输入电压和第一电容器上的电压电势之和中减去第二电容器两端的电压电势，以生成输出电压。以这种方式操作，第一，第二和第三电容器将提供期望的2 / 3x电压倍增。这种相对较低的倍增因数在需要2.5V和1.8V电源的集成电路应用中尤其有用，特别是在输入电压由锂电池提供的情况下更是如此。

4. 发明申请

WO2008030796A3 SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY 审中-公开
标题翻译：可扩展的电可擦除和可编程内存
公开(公告)号：WO2008030796A3
公开(公告)日：2008-05-02
申请号：PCT/US2007077514
申请日：2007-09-04
申请人： CATALYST SEMICONDUCTOR INC , GEORGESCU SORIN S , COSMIN PETER , SMARANDOIU GEORGE
发明人： GEORGESCU SORIN S , COSMIN PETER , SMARANDOIU GEORGE
IPC分类号： H01L29/788
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
摘要翻译：包含一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管并存储两个数据位，有效地提供了一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储器晶体管，第二非易失性存储器晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储器晶体管的源极区域连续的第二源极区域以及向下延伸穿过第一阱区域以接触第二阱区域的漏极区域。第一，第二和第三半导体区域和第二阱区域具有第一导电类型，并且第一阱区域具有与第一导电类型相反的第二导电类型。

5. 发明申请

WO2009117219A1 SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY 审中-公开
标题翻译：可拆卸电可擦除和可编程存储器
公开(公告)号：WO2009117219A1
公开(公告)日：2009-09-24
申请号：PCT/US2009/034973
申请日：2009-02-24
申请人： CATALYST SEMICONDUCTOR, INC. , GEORGESCU, Sorin S. , COSMIN, A. Peter , SMARANDOIU, George
发明人： GEORGESCU, Sorin S. , COSMIN, A. Peter , SMARANDOIU, George
IPC分类号： H01L29/00
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/823857 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和与位于与EEPROM单元对相同行的其它非易失性存储器晶体管的源极区域连续的第三源极区域。

6. 发明申请

WO2008148065A1 NON-VOLATILE MEMORY WITH HIGH RELIABILITY 审中-公开
标题翻译：具有高可靠性的非易失性存储器
公开(公告)号：WO2008148065A1
公开(公告)日：2008-12-04
申请号：PCT/US2008/064798
申请日：2008-05-23
申请人： CATALYST SEMICONDUCTOR, INC. , COSMIN, A., Peter , GEORGESCU, Sorin, S. , SMARANDOIU, George , TACHE, Adrian, M.
发明人： COSMIN, A., Peter , GEORGESCU, Sorin, S. , SMARANDOIU, George , TACHE, Adrian, M.
IPC分类号： G11C11/34
CPC分类号： G11C16/0433
摘要： A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during the erase and programming phases. The access transistors are turned on and the source select transistors turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
摘要翻译：非易失性存储器（NVM）系统包括一组NVM单元，每个NVM单元包括：NVM晶体管; 将NVM晶体管耦合到对应的位线的存取晶体管; 以及将NVM晶体管耦合到公共源的源极选择晶体管。 NVM单元由包括擦除阶段和程序阶段的两相操作来写入。在擦除和编程阶段期间，将一组常见的位线电压施加到位线。访问晶体管导通，并且在擦除和编程阶段期间，源选择晶体管截止。在擦除阶段期间，将第一控制电压施加到NVM晶体管的控制栅极，并且在编程阶段期间将第二控制电压施加到NVM晶体管的控制栅极。在这些情况下，Fowler-Nordheim隧道运行的平均需求数量减少。

7. 发明申请

WO2008070578A3 METHOD FOR REDUCING CHARGE LOSS IN ANALOG FLOATING GATE CELL 审中-公开
标题翻译：降低模拟浮动栅极单元中的电荷损失的方法
公开(公告)号：WO2008070578A3
公开(公告)日：2008-08-28
申请号：PCT/US2007086175
申请日：2007-11-30
申请人： CATALYST SEMICONDUCTOR INC , SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
发明人： SPOREA RADU A , GEORGESCU SORIN S , POENARU ILIE MARIAN I
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
摘要翻译：电压参考电路响应于第一非易失性存储器（NVM）晶体管的编程的阈值电压来提供参考电压。第一NVM晶体管的阈值电压通过将编程电压施加到与第一NVM晶体管共享浮置栅极的隧穿电容器的公共连接的源极/漏极区域来编程。在电压参考电路的正常操作期间，隧穿电容器的源极/漏极区域连接到第二NVM晶体管，该第二NVM晶体管具有与第一NVM晶体管的浮置栅极相同的电和热特性。结果，来自第一NVM晶体管的浮置栅极的电荷损失有利地被最小化。

8. 发明申请

WO2008070578A2 METHOD FOR REDUCING CHARGE LOSS IN ANALOG FLOATING GATE CELL 审中-公开
标题翻译：用于减少模拟浮选室中电荷损失的方法
公开(公告)号：WO2008070578A2
公开(公告)日：2008-06-12
申请号：PCT/US2007/086175
申请日：2007-11-30
申请人： CATALYST SEMICONDUCTOR, INC. , SPOREA, Radu A. , GEORGESCU, Sorin S. , POENARU, Ilie Marian I.
发明人： SPOREA, Radu A. , GEORGESCU, Sorin S. , POENARU, Ilie Marian I.
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
摘要翻译：电压参考电路响应于第一非易失性存储器（NVM）晶体管的编程阈值电压提供参考电压。通过将编程电压施加到隧道电容器的公共连接的源极/漏极区域来编程第一NVM晶体管的阈值电压，隧道电容器与第一NVM晶体管共享浮置栅极。在电压参考电路的正常工作期间，隧道电容器的源/漏区连接到具有与第一NVM晶体管的浮置栅极相同的电和热特性的第二NVM晶体管。结果，有利地最小化了来自第一NVM晶体管的浮置栅极的电荷损耗。

9. 发明申请

WO2008030796A2 SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY 审中-公开
标题翻译：可扩展的电可擦除和可编程内存
公开(公告)号：WO2008030796A2
公开(公告)日：2008-03-13
申请号：PCT/US2007/077514
申请日：2007-09-04
申请人： CATALYST SEMICONDUCTOR, INC. , GEORGESCU, Sorin S. , COSMIN, Peter , SMARANDOIU, George
发明人： GEORGESCU, Sorin S. , COSMIN, Peter , SMARANDOIU, George
IPC分类号： H01L29/788
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管并存储两个数据位，有效地提供了一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储器晶体管，第二非易失性存储器晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储器晶体管的源极区域连续的第二源极区域以及向下延伸穿过第一阱区域以接触第二阱区域的漏极区域。第一，第二和第三半导体区域和第二阱区域具有第一导电类型，并且第一阱区域具有与第一导电类型相反的第二导电类型。

10. 发明申请

WO2008103835A3 FRACTIONAL CHARGE PUMP FOR STEP-DOWN DC-DC CONVERTER 审中-公开
标题翻译：用于降压DC-DC转换器的分体充电泵
公开(公告)号：WO2008103835A3
公开(公告)日：2008-10-16
申请号：PCT/US2008054596
申请日：2008-02-21
申请人： CATALYST SEMICONDUCTOR INC , GEORGESCU SORIN S , RUSSELL ANTHONY G , BARTHOLOMEUEZ CHRIS
发明人： GEORGESCU SORIN S , RUSSELL ANTHONY G , BARTHOLOMEUEZ CHRIS
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a multiplication factor of 2/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the output terminal is connected to the common node of the first and second capacitors. In a third mode, the voltage potential across the second capacitor is subtracted from the sum of the input voltage and the voltage potential across the first capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 2/3x voltage multiplication. This relatively low multiplication factor can be beneficial in applications requiring 2.5V and 1.8V supplies for integrated circuits, particularly where the input voltage is provided by a lithium battery.
摘要翻译：电荷泵通过使用三相工作模式提供2/3的倍增系数。在第一模式中，第一和第二电容器从输入电压充电，而第三电容器基于第三电容器中存储的电荷来驱动输出电压。在第二模式中，输出端子连接到第一和第二电容器的公共节点。在第三模式中，从第一电容器两端的输入电压和电压电平之和减去第二电容器两端的电压电位，以产生输出电压。以这种方式操作，第一，第二和第三电容器将提供期望的2 / 3x电压倍增。这种相对较低的乘法因子对于集成电路需要2.5V和1.8V电源的应用可能是有益的，特别是在输入电压由锂电池提供的情况下。

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