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    • 2. 发明申请
    • BIOMARKER SENSORS AND METHOD FOR MULTI-COLOR IMAGING AND PROCESSING OF SINGLE-MOLECULE LIFE SIGNATURES
    • 生物标记传感器和多色成像和单分子生命信号处理方法
    • WO2007046819A2
    • 2007-04-26
    • PCT/US2005/041954
    • 2005-11-15
    • CALIFORNIA INSTITUE OF TECHNOLOGYWADE, Lawarence, A.COLLIER, Charles, Patrick
    • WADE, Lawarence, A.COLLIER, Charles, Patrick
    • C12Q1/68C12M1/34C12M3/00
    • G01Q60/42G01Q80/00
    • A device comprising an array of active regions for use in reacting one or more species in at least two of the active regions in a sequential process, e.g., sequential reactions. The device has a transparent substrate member, which has a surface region. The device has a silane material overlying the surface region. The device has a first active region formed overlying a first portion of the silane material. In a specific embodiment, the first active region has a first dimension of less than 1 micron in size and has one or more first molecules capable of binding to the first portion of the silane material. In a specific embodiment, the device has a second active region formed overlying a second portion of the silane material. The second active region has a second dimension of less than 1 micron in size and has one or more second molecules capable of binding to the second portion of the active region. In a specific embodiment, the device has a spatial distance separating the first active region and the second active region. In a preferred embodiment, the spatial distance is characterized by a dimension of 1 micron and less. The device has a fluid material in contact with the first active region, the second active region, and the spatial distance according to a specific embodiment. The device also has a reactant species within the fluid material. The reactant species is capable of spatially moving from the first active region to the second active region over the spatial distance of 1 micron and less within a time of less than 10 microseconds.
    • 一种包含活性区域阵列的装置,其用于在顺序过程(例如顺序反应)中使至少两个活性区域中的一种或多种物质反应。 该装置具有透明基板部件,该基板部件具有表面区域。 该装置具有覆盖表面区域的硅烷材料。 该装置具有覆盖硅烷材料的第一部分的第一有源区。 在具体实施方案中,第一有源区具有尺寸小于1微米的第一尺寸,并具有一个或多个能够结合硅烷材料的第一部分的第一分子。 在具体实施方案中,该装置具有覆盖硅烷材料的第二部分的第二有源区。 第二有源区具有尺寸小于1微米的第二维度,并且具有一个或多个能够结合活性区的第二部分的第二分子。 在具体实施例中,该装置具有分隔第一有源区和第二有源区的空间距离。 在优选实施例中,空间距离的特征在于1微米和更小的尺寸。 根据具体实施例,该装置具有与第一有源区域,第二有源区域和空间距离接触的流体材料。 该装置还在流体材料内具有反应物种类。 反应物种能够在小于10微秒的时间内在空间距离为1微米以下的空间距离上从第一有源区域移动到第二有源区域。
    • 8. 发明授权
    • Gallium arsenide source follower FET logic family with diodes for
preventing leakage currents
    • 砷化镓源极跟随器FET逻辑系列具有防止漏电流的二极管
    • US5451890A
    • 1995-09-19
    • US225518
    • 1994-04-11
    • Alain J. MartinJose A. TiernoBrian Von Herzen
    • Alain J. MartinJose A. TiernoBrian Von Herzen
    • H03K19/0952H03K19/0956
    • H03K19/0952
    • The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connected in series through a level-shifting Schottky diode with the source-to-drain channel of an depletion mode pull-down FET between drain and source voltage rails. The source of the pull-up FET is connected to the diode's anode while the drain of the pull-down FET is connected to the diode's cathode and is the output node of the input logic switching stage. The level-shifting diode isolates the output node from the input node, which allows the input voltage to switch rail-to-rail without causing problems. The voltage between the source and drain rails is selected so that the Schottky barrier gate of the enhancement mode pull-up transistor is barely forward biased over the threshold voltage of the Schottky barrier gate junction, so that there is very little current through the gate. The second stage is an inverting stage having an enhancement mode pull-up transistor and a depletion mode pull-down transistor whose source-to-drain channels are connected in series across the source and drain voltage rails. The gate of the pull down transistor is connected to the output node of the logic switching stage, while the source-to-drain connection between the two transistors is the output node of the gate.
    • 本发明的基本构造块是由两个阶段组成的反相器门:第一级是由耗尽型上拉FET组成的输入逻辑开关级,其栅极是输入节点并且源极 - 漏极通道连接 通过电平移位肖特基二极管串联,在漏极和源极电压轨之间具有耗尽型下拉FET的源极到漏极通道。 上拉FET的源极连接到二极管的阳极,而下拉FET的漏极连接到二极管的阴极,并且是输入逻辑开关级的输出节点。 电平移位二极管将输出节点与输入节点隔离,这允许输入电压切换轨到轨而不会引起问题。 选择源极和漏极之间的电压,使得增强模式上拉晶体管的肖特基势垒栅极不会在肖特基势垒栅极结的阈值电压上正向偏置,使得通过栅极的电流非常小。 第二级是具有增强型上拉晶体管和耗尽型下拉晶体管的反相级,其源极至漏极通道串联连接在源极和漏极电压轨道上。 下拉晶体管的栅极连接到逻辑开关级的输出节点,而两个晶体管之间的源极到漏极连接是栅极的输出节点。