专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06825098B2 Method for fabricating microstructures and arrangement of microstructures 有权
标题翻译：微结构的制作方法及微观结构的布置
公开(公告)号：US06825098B2
公开(公告)日：2004-11-30
申请号：US10606069
申请日：2003-06-25
申请人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
发明人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
IPC分类号： H10L2130
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
摘要翻译：称为“细胞镶嵌方法”的方法利用在图案化层中产生的多个规则排列的称为“单元”的闭合空腔。空腔的尺寸在待生产的微结构的数量级上。通过提供掩模来打开选定的空腔，并移除位于相邻的开放空腔之间的隔板，以提供用待制造的微结构材料填充的沟槽和孔。通过化学机械抛光步骤去除突起材料。微结构尤其是集成电路的互连和接触孔。

2. 发明申请

US20050054184A1 Method for fabricating microstructures and arrangement of microstructures 失效
标题翻译：微结构的制作方法及微观结构的布置
公开(公告)号：US20050054184A1
公开(公告)日：2005-03-10
申请号：US10972804
申请日：2004-10-25
申请人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
发明人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
IPC分类号： H01L21/768 , H01L23/522 , H01L21/8242 , H01L21/44
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
摘要翻译：称为“细胞镶嵌方法”的方法利用在图案化层中产生的多个规则排列的称为“单元”的闭合空腔。空腔的尺寸在待生产的微结构的数量级上。通过提供掩模来打开选定的空腔，并移除位于相邻的开放空腔之间的隔板，以提供用待制造的微结构材料填充的沟槽和孔。通过化学机械抛光步骤去除突起材料。微结构尤其是集成电路的互连和接触孔。

3. 发明授权

US07023063B2 Arrangement of microstructures 失效
标题翻译：微结构布置
公开(公告)号：US07023063B2
公开(公告)日：2006-04-04
申请号：US10972804
申请日：2004-10-25
申请人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
发明人： Zvonimir Gabric , Werner Pamler , Siegfried Schwarzl
IPC分类号： H01L31/113
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.
摘要翻译：称为“细胞镶嵌方法”的方法利用在图案化层中产生的多个规则排列的称为“单元”的闭合空腔。空腔的尺寸在待生产的微结构的数量级上。通过提供掩模来打开选定的空腔，并移除位于相邻的开放空腔之间的隔板，以提供用待制造的微结构材料填充的沟槽和孔。通过化学机械抛光步骤去除突起材料。微结构尤其是集成电路的互连和接触孔。

4. 发明授权

US07259441B2 Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit 有权
标题翻译：集成电路中的空心结构和在集成电路中制造这种中空结构的方法
公开(公告)号：US07259441B2
公开(公告)日：2007-08-21
申请号：US10469279
申请日：2002-02-15
申请人： Werner Pamler , Siegfried Schwarzl , Zvonimir Gabric
发明人： Werner Pamler , Siegfried Schwarzl , Zvonimir Gabric
IPC分类号： H01L29/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface. Adjacent lands with spaces are formed from the second layer and the third layer. A third isolation material is selectively applied on the adjacent lands to the third layer, such that a fourth layer is formed between and above the adjacent lands. Parallel to the first layer surface, the fourth layer is partially removed until the second layer surface is uncovered. The fourth layer is completely removed above some spaces, and finally these spaces are filled with electrically conductive material in order to form electrical contacts between the first layer surface and the second layer surface, resulting in a pattern of voids.
摘要翻译：具有第一层，第一层表面和第一层表面上的相邻焊盘的集成电路中的空隙图案，相邻焊盘包围空间并且包括第二层第一隔离材料和第三层第二隔离材料布置在第二层上。空隙的图案具有第四隔离材料的第四层，其封闭至少一些空间并且不能沉积在第一隔离材料上。第四层布置在第三层上并具有第二层表面。未被第四层封闭的空间用导电材料填充。在集成电路中产生空隙图案的方法中，将第一隔离材料的第二层施加到第一层的第一层表面。将第三隔离材料层施加到第二层上，第三层获得平行于第一层表面布置的第二层表面。从第二层和第三层形成具有空间的相邻区域。第三隔离材料被选择性地施加到相邻的焊盘上到第三层，使得在相邻的焊盘之间和之上形成第四层。与第一层表面平行，第四层被部分去除，直到第二层表面未被覆盖。第四层在一些空间之上完全除去，最后这些空间填充有导电材料，以形成第一层表面和第二层表面之间的电接触，导致空隙图案。

5. 发明授权

US06686643B2 Substrate with at least two metal structures deposited thereon, and method for fabricating the same 有权
标题翻译：具有沉积在其上的至少两种金属结构的基板及其制造方法
公开(公告)号：US06686643B2
公开(公告)日：2004-02-03
申请号：US09725346
申请日：2000-11-29
申请人： Siegfried Schwarzl , Werner Pamler , Zvonimir Gabric
发明人： Siegfried Schwarzl , Werner Pamler , Zvonimir Gabric
IPC分类号： H01L2900
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： Metal structures that can be produced by a damascene process are disposed in a first insulating layer and a second insulating layer is disposed above the latter. There is in each case at least one cavity which is disposed between the metal structures, is disposed in the first insulating layer and is covered by the second insulating layer. The cavities and the metal structures are produced next to one another by self-aligned process steps.
摘要翻译：可以通过镶嵌工艺制造的金属结构设置在第一绝缘层中，并且第二绝缘层设置在第二绝缘层的上方。在每种情况下，设置在金属结构之间的至少一个空腔设置在第一绝缘层中并被第二绝缘层覆盖。腔和金属结构通过自对准工艺步骤彼此相邻地制造。

6. 发明申请

US20070120263A1 Conductor track arrangement and associated production method 审中-公开
标题翻译：导体轨迹布置及相关生产方法
公开(公告)号：US20070120263A1
公开(公告)日：2007-05-31
申请号：US11506570
申请日：2006-08-18
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Andreas Stich
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Andreas Stich
IPC分类号： H01L23/48
CPC分类号： H01L21/7682
摘要： A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.
摘要翻译：导体轨道布置包括衬底，至少两个导体轨道，空腔和覆盖导体轨道并封闭空腔的抗蚀剂层。通过形成宽度小于导体轨道的宽度的载体轨道，还可以在导体轨道下方横向形成气隙，以便以自对准方式减小耦合电容和信号延迟。

7. 发明授权

US07755160B2 Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly 有权
标题翻译：等离子体激发化学气相沉积法硅/氧/含氮材料和分层组装
公开(公告)号：US07755160B2
公开(公告)日：2010-07-13
申请号：US10586788
申请日：2005-01-22
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler
IPC分类号： H01L21/314 , H01L21/469
CPC分类号： H01L21/764 , C23C16/308 , H01L21/3145 , H01L21/76801 , H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.
摘要翻译：公开了一种制造层布置的方法。在具有多个导电结构和/或导电结构的一部分表面上的衬底上形成一层氧材料和氮材料。使用等离子体增强化学气相沉积工艺形成该层，其中在通过有机硅前体材料供应硅材料和氧材料期间供给氮材料。氧材料层和氮材料层以这样的方式形成，使得在导电结构之间保留没有材料的区域。在氧材料层和氮材料层上形成包括电绝缘材料的中间层。在中间层上选择性地形成覆盖层，使得在导电结构之间没有材料的区域与环境密封并形成空腔。

8. 发明申请

US20070246831A1 Method for manufacturing a layer arrangement and layer arrangement 有权
标题翻译：制造层布置和层布置的方法
公开(公告)号：US20070246831A1
公开(公告)日：2007-10-25
申请号：US11786770
申请日：2007-04-12
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
摘要翻译：在制造层布置的方法中，多个导电结构嵌入基板中。至少在相邻的导电结构之间去除衬底的材料。在每个导电结构的侧壁的至少一部分上形成中间层。第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。

9. 发明授权

US07807563B2 Method for manufacturing a layer arrangement and layer arrangement 有权
标题翻译：制造层布置和层布置的方法
公开(公告)号：US07807563B2
公开(公告)日：2010-10-05
申请号：US11786770
申请日：2007-04-12
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
IPC分类号： H01L23/58
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
摘要翻译：在制造层布置的方法中，多个导电结构嵌入基板中。至少在相邻的导电结构之间去除衬底的材料。在每个导电结构的侧壁的至少一部分上形成中间层。第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。

10. 发明授权

US07033926B2 Strip conductor arrangement and method for producing a strip conductor arrangement 失效
标题翻译：带状导体布置及其制造方法
公开(公告)号：US07033926B2
公开(公告)日：2006-04-25
申请号：US10487190
申请日：2002-08-09
申请人： Günther Schindler , Werner Pamler , Zvonimir Gabric
发明人： Günther Schindler , Werner Pamler , Zvonimir Gabric
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.
摘要翻译：互连装置包括由具有衬底表面的第一绝缘材料制成的衬底，在衬底中彼此相邻布置的至少两个互连件，由衬底上方的第二绝缘材料制成的缓冲层，并且包括缓冲层平行于衬底表面的表面，布置在互连件之间的至少一个空腔相对于缓冲层表面比互连件更深地延伸到衬底中，并且由第三绝缘体制成的覆盖层材料，其布置在缓冲层上方并相对于缓冲层表面完全封闭空腔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式