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1. 发明授权

US08650327B2 Processor with programmable virtual ports 有权
标题翻译：具有可编程虚拟端口的处理器
公开(公告)号：US08650327B2
公开(公告)日：2014-02-11
申请号：US13604639
申请日：2012-09-06
申请人： Shixiang Nie , Zhijun Chen , Zhihong Cheng
发明人： Shixiang Nie , Zhijun Chen , Zhihong Cheng
IPC分类号： G06F3/00
CPC分类号： G06F15/7867
摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
摘要翻译：具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

2. 发明授权

US08569992B2 Stepper motor controller and method for controlling same 有权
标题翻译：步进电机控制器及其控制方法
公开(公告)号：US08569992B2
公开(公告)日：2013-10-29
申请号：US13047801
申请日：2011-03-15
申请人： Zhihong Cheng , Zhijun Chen , Shixiang Nie
发明人： Zhihong Cheng , Zhijun Chen , Shixiang Nie
IPC分类号： H02P8/00
CPC分类号： H02P8/12
摘要： A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.
摘要翻译：步进电机控制器包括具有控制输出的控制电路和具有单独驱动器PWM输出的单独的驱动器脉宽调制（PWM）电路和耦合到控制输出的调制控制输入。存在一组单独的驱动器，每个驱动器具有耦合到一个PWM输出的输入，以及耦合到控制器的单独驱动器端子的输出。有普通驱动器PWM电路具有公共驱动器PWM输出。具有公共驱动器输入的公共驱动器耦合到公共驱动器PWM输出，并且公共驱动器输出耦合到控制器的公共驱动器端子。当线圈连接在相应的驱动器端子和公共驱动器端子之间时，各个驱动器端子将各个PWM驱动器电流提供给线圈，并且公共的驱动器电流从公共驱动器端子提供给线圈。

3. 发明申请

US20130147534A1 MASTER SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION 审中-公开
标题翻译：主要从事低功耗的飞溅
公开(公告)号：US20130147534A1
公开(公告)日：2013-06-13
申请号：US13605984
申请日：2012-09-06
申请人： Zhihong Cheng , Shixiang Nie , Yang Wang
发明人： Zhihong Cheng , Shixiang Nie , Yang Wang
IPC分类号： H03K3/289
CPC分类号： H03K3/35625 , H03K3/012
摘要： In a master-slave D flip-flop, the master latch has first and second three-state stages and a feedback stage for positive feedback from the data outputs of the first and second three-state stages to the data input of the second three-state stage. The slave latch has third and fourth three-state stages and a feedback stage for positive feedback from the data outputs of the third and fourth three-state stages to the data input of the fourth three-state stage. Clock signals are applied from a clock signal source to the clock inputs of a clock switch element in one of the three-state stages whose clock signal is shared with another of the three-state stages, reducing the number of clock switches and clock switch power consumption. Data inverters also may be shared between a three-state stage of the master latch and a three-state stage of the slave latch.
摘要翻译：在主从D触发器中，主锁存器具有第一和第二三态级以及用于从第一和第二三态级的数据输出到第二三态的数据输入的正反馈的反馈级，状态。从锁存器具有第三和第四三状态级以及用于从第三和第四三态级的数据输出到第四三态级的数据输入的正反馈的反馈级。时钟信号从时钟信号源施加到时钟信号与时钟信号与另一个三态级共享的三态级之一的时钟切换元件的时钟输入，减少时钟切换次数和时钟切换功率消费。数据逆变器也可以在主锁存器的三态级与从锁存器的三态级之间共享。

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