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1. 发明申请

US20140096103A1 SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER 有权
标题翻译：用于优化在WAFER上生产的DIES数量的系统
公开(公告)号：US20140096103A1
公开(公告)日：2014-04-03
申请号：US13723207
申请日：2012-12-21
申请人： Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
发明人： Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G03F7/70433 , G06F2217/12 , Y02P90/265
摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
摘要翻译：用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中，具有TDA的最大数量的模具。可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表，和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

2. 发明授权

US08671381B1 System for optimizing number of dies produced on a wafer 有权
标题翻译：用于优化在晶片上生产的模具数量的系统
公开(公告)号：US08671381B1
公开(公告)日：2014-03-11
申请号：US13723207
申请日：2012-12-21
申请人： Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
发明人： Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G03F7/70433 , G06F2217/12 , Y02P90/265
摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
摘要翻译：用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中，具有TDA的最大数量的模具。可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表，和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

3. 发明申请

US20130111099A1 PROCESSOR WITH PROGRAMMABLE VIRTUAL PORTS 有权
标题翻译：具有可编程虚拟端口的处理器
公开(公告)号：US20130111099A1
公开(公告)日：2013-05-02
申请号：US13604639
申请日：2012-09-06
申请人： Shixiang NIE , Zhijun Chen , Zhihong Cheng
发明人： Shixiang NIE , Zhijun Chen , Zhihong Cheng
IPC分类号： G06F13/40
CPC分类号： G06F15/7867
摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
摘要翻译：具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

4. 发明授权

US09148149B2 Flip-flop circuit with resistive poly routing 有权
标题翻译：具有电阻多路由的触发器电路
公开(公告)号：US09148149B2
公开(公告)日：2015-09-29
申请号：US14176025
申请日：2014-02-07
申请人： Zhihong Cheng , Peidong Wang
发明人： Zhihong Cheng , Peidong Wang
IPC分类号： H03K3/289 , H03K19/094 , H03K3/3562
CPC分类号： H03K19/09429 , H03K3/35625
摘要： A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
摘要翻译：锁存电路具有共享相同互补控制的三态栅极和反向三态栅极。当三态门关闭时，反向三态门锁定三态门的输出。互补控制信号包括第一未掺杂多晶硅条。反向三态栅极的输出可以经由第二未掺杂多晶硅条耦合到三态栅极的输出端。

5. 发明授权

US08650327B2 Processor with programmable virtual ports 有权
标题翻译：具有可编程虚拟端口的处理器
公开(公告)号：US08650327B2
公开(公告)日：2014-02-11
申请号：US13604639
申请日：2012-09-06
申请人： Shixiang Nie , Zhijun Chen , Zhihong Cheng
发明人： Shixiang Nie , Zhijun Chen , Zhihong Cheng
IPC分类号： G06F3/00
CPC分类号： G06F15/7867
摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
摘要翻译：具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

6. 发明授权

US09166585B2 Low power inverter circuit 有权
标题翻译：低功率逆变电路
公开(公告)号：US09166585B2
公开(公告)日：2015-10-20
申请号：US14463673
申请日：2014-08-20
申请人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
IPC分类号： H03K19/003 , H03K19/00 , H03K19/017 , H03K19/20
CPC分类号： H03K19/0013 , H03K19/0016 , H03K19/003 , H03K19/017 , H03K19/01707 , H03K19/20
摘要： A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
摘要翻译：低功率逆变器电路包括在其栅极端子处接收输入信号的第一和第二晶体管。第一和第二晶体管分别通过其源极端子连接到第三和第四晶体管。第三和第四晶体管分别与第五和第六晶体管并联连接。第三和第四晶体管被连续接通，并且当输入信号从一个状态转变到另一个状态时，第五和第六晶体管以这样的方式被控制，以减少流过第一和第二晶体管的短路电流。

7. 发明授权

US08941429B2 Master-slave flip-flop with low power consumption 有权
标题翻译：主从触发器具有低功耗
公开(公告)号：US08941429B2
公开(公告)日：2015-01-27
申请号：US13959745
申请日：2013-08-06
申请人： Zhihong Cheng
发明人： Zhihong Cheng
IPC分类号： H03K3/356 , H03K3/012 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/35625
摘要： In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
摘要翻译：在主从触发器中，主锁存器具有第一和第二三态级以及第一反馈级。从锁存器具有第三和第四三状态级和第二反馈级。提供具有相反相位的第一和第二时钟开关。第一时钟切换器配置在第一和第四三状态级之一中，另一级共享第一时钟切换。第二时钟切换器配置在第二和第三三状态级之一中，另一级共享第二时钟切换。第二三状态级具有附加的互补器件对，其具有彼此串联连接的信号路径，两者都由从锁存器的数据输出选通。触发器可减少时钟切换的数量和时钟切换功耗。

8. 发明申请

US20140285236A1 FLIP-FLOP CIRCUIT WITH RESISTIVE POLY ROUTING 有权
标题翻译：具有电阻多路径的FLIP-FLOP电路
公开(公告)号：US20140285236A1
公开(公告)日：2014-09-25
申请号：US14176025
申请日：2014-02-07
申请人： Zhihong Cheng , Peidong Wang
发明人： Zhihong Cheng , Peidong Wang
IPC分类号： H03K19/094
CPC分类号： H03K19/09429 , H03K3/35625
摘要： A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
摘要翻译：锁存电路具有共享相同互补控制的三态门和反向三态门。当三态门关闭时，反向三态门锁定三态门的输出。互补控制信号包括第一未掺杂多晶硅条。反向三态栅极的输出可以经由第二未掺杂多晶硅条耦合到三态栅极的输出端。

9. 发明申请

US20140240017A1 MASTER-SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION 有权
标题翻译：主要采用低功耗的飞溅
公开(公告)号：US20140240017A1
公开(公告)日：2014-08-28
申请号：US13959745
申请日：2013-08-06
申请人： Zhihong Cheng
发明人： Zhihong Cheng
IPC分类号： H03K3/012
CPC分类号： H03K3/012 , H03K3/35625
摘要： In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
摘要翻译：在主从触发器中，主锁存器具有第一和第二三态级以及第一反馈级。从锁存器具有第三和第四三状态级和第二反馈级。提供具有相反相位的第一和第二时钟开关。第一时钟切换器配置在第一和第四三状态级之一中，另一级共享第一时钟切换。第二时钟切换器配置在第二和第三三状态级之一中，另一级共享第二时钟切换。第二三状态级具有附加的互补器件对，其具有彼此串联连接的信号路径，两者都由从锁存器的数据输出选通。触发器可减少时钟切换的数量和时钟切换功耗。

10. 发明授权

US08569992B2 Stepper motor controller and method for controlling same 有权
标题翻译：步进电机控制器及其控制方法
公开(公告)号：US08569992B2
公开(公告)日：2013-10-29
申请号：US13047801
申请日：2011-03-15
申请人： Zhihong Cheng , Zhijun Chen , Shixiang Nie
发明人： Zhihong Cheng , Zhijun Chen , Shixiang Nie
IPC分类号： H02P8/00
CPC分类号： H02P8/12
摘要： A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.
摘要翻译：步进电机控制器包括具有控制输出的控制电路和具有单独驱动器PWM输出的单独的驱动器脉宽调制（PWM）电路和耦合到控制输出的调制控制输入。存在一组单独的驱动器，每个驱动器具有耦合到一个PWM输出的输入，以及耦合到控制器的单独驱动器端子的输出。有普通驱动器PWM电路具有公共驱动器PWM输出。具有公共驱动器输入的公共驱动器耦合到公共驱动器PWM输出，并且公共驱动器输出耦合到控制器的公共驱动器端子。当线圈连接在相应的驱动器端子和公共驱动器端子之间时，各个驱动器端子将各个PWM驱动器电流提供给线圈，并且公共的驱动器电流从公共驱动器端子提供给线圈。

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