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1. 发明授权

US06368979B1 Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure 有权
公开(公告)号：US06368979B1
公开(公告)日：2002-04-09
申请号：US09607511
申请日：2000-06-28
申请人： Zhihai Wang , Wilbur G. Catabay , Joe W. Zhao
发明人： Zhihai Wang , Wilbur G. Catabay , Joe W. Zhao
IPC分类号： H01L2100
CPC分类号： H01L21/7681 , H01L21/31116 , H01L21/31144 , H01L21/76813
摘要： A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask. The first photoresist mask (the via mask) is, therefore, removed during the formation of the first hard mask, instead of in a separate oxidizing step which would damage the low k dielectric material. Damage to the low k dielectric material during removal of the second photoresist mask (the trench mask) is also avoided by depositing a second layer of low k dielectric material over the first hard mask; forming over the second layer of low k dielectric material a second hard mask layer; forming over the second hard mask layer a second photoresist mask having a pattern of trench openings therein; and then forming the second hard mask by etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein, using at etch system which will also remove the second photoresist mask. Thus, the second photoresist mask (the trench mask) is also removed during the formation of the second hard mask, instead of in a separate oxidizing step which would damage the low k dielectric material.

2. 发明授权

US6028015A Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption 有权
标题翻译：处理低介电常数有机氧化硅绝缘材料损伤表面以抑制吸湿的方法
公开(公告)号：US6028015A
公开(公告)日：2000-02-22
申请号：US281514
申请日：1999-03-29
申请人： Zhihai Wang , Wilbur G. Catabay , Joe W. Zhao
发明人： Zhihai Wang , Wilbur G. Catabay , Joe W. Zhao
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/3105 , H01L21/3122 , H01L21/76814 , H01L21/76831
摘要： A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.
摘要翻译：描述了一种处理集成电路结构的低介电常数有机氧化硅绝缘层的损伤表面以抑制水分吸收的方法，其包括用氢等离子体处理所述有机氧化硅绝缘层的这种损坏表面。用氢等离子体处理可以使有机硅氧化物层受损表面的氢键键合到具有悬挂键的硅原子上，以取代被损坏的表面从这种硅原子上切下的有机材料，从而吸收有机物损坏表面的水分通过这种硅悬挂键与水分的结合，氧化硅层被抑制。

3. 发明授权

US5660682A Plasma clean with hydrogen gas 失效
标题翻译：用氢气清洗等离子体
公开(公告)号：US5660682A
公开(公告)日：1997-08-26
申请号：US615437
申请日：1996-03-14
申请人： Joe W. Zhao , Zhihai Wang , Wilbur G. Catabay
发明人： Joe W. Zhao , Zhihai Wang , Wilbur G. Catabay
IPC分类号： H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/461
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76814
摘要： A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.
摘要翻译：从集成电路中去除材料的方法。将集成电路放置在反应室内，并且将氩气和氢气流引入反应室中，其中氢气流量大于氩气流量。氩气和氢气的流动被激发以形成等离子体，并且通过材料与激励的氩气和氢气流的反应将材料从集成电路移除，以形成气态产物，其被泵出反应室。当去除所需量的材料时，停止等离子体和氩气和氢气的流动，并且将集成电路从反应室中取出。

4. 发明授权

US5770520A Method of making a barrier layer for via or contact opening of integrated circuit structure 失效
标题翻译：制造集成电路结构的通孔或接触开口的阻挡层的方法
公开(公告)号：US5770520A
公开(公告)日：1998-06-23
申请号：US760466
申请日：1996-12-05
申请人： Joe W. Zhao , Zhihai Wang , Wilbur G. Catabay
发明人： Joe W. Zhao , Zhihai Wang , Wilbur G. Catabay
IPC分类号： C23C16/42 , C23C16/34 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76843 , C23C16/34
摘要： Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistivity of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of grain boundaries which are believed to provide the diffusion path through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti--Si--N material formed using a source of titanium, a source of silicon, and a source of nitrogen. None of the source materials should contain oxygen to avoid formation of undesirable oxides which would increase the resistivity of the barrier layer. In a particularly preferred embodiment, an organic source of titanium is used, and either or both of the silicon and nitrogen sources are capable of reacting with the organic portion of the organic titanium reactant to form gaseous byproducts which can then be removed from the deposition chamber to inhibit the formation of carbon deposits in the chamber or on the integrated circuit structure.
摘要翻译：描述了集成电路结构中的阻挡层，其形成在下面的材料中的通孔或接触开口中，其中下面的材料（或沉积在阻挡层上的填充材料）通过阻挡层的扩散被抑制，而不会不适当地增加阻挡层的厚度和电阻率。这通过用无定形材料代替结晶氮化钛来实现，从而消除据信提供通过氮化钛材料的扩散路径的晶界的存在。在优选实施例中，非晶形阻挡层包括使用钛源，硅源和氮源形成的无定形三元Ti-Si-N材料。源材料都不应含有氧，以避免形成不希望的氧化物，这会增加阻挡层的电阻率。在一个特别优选的实施方案中，使用有机钛源，并且硅和氮源中的任一种或两者能够与有机钛反应物的有机部分反应以形成气态副产物，然后可以从沉积室以抑制室内或集成电路结构上的碳沉积物的形成。

5. 发明授权

US06232658B1 Process to prevent stress cracking of dielectric films on semiconductor wafers 有权
标题翻译：防止半导体晶片上电介质膜发生应力开裂的工艺
公开(公告)号：US06232658B1
公开(公告)日：2001-05-15
申请号：US09346493
申请日：1999-06-30
申请人： Wilbur G. Catabay , Wei-Jen Hsia , Joe W. Zhao
发明人： Wilbur G. Catabay , Wei-Jen Hsia , Joe W. Zhao
IPC分类号： H01L2353
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/56 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L21/02362 , H01L21/31612 , H01L21/76828 , H01L21/76832 , Y10S438/981
摘要： The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive. The steps of depositing an additional thin dielectric layer and then exposing the semiconductor wafer to an elevated temperature may be repeated until a sufficient composite thickness of dielectric material has been formed, typically about 5000 Å to about 10,000 Å.
摘要翻译：本发明包括一种在沉积到集成电路结构上的层中形成具有压应力的电介质膜的方法。该方法包括将第一薄层电介质材料沉积到集成电路结构上，然后将集成电路结构暴露于升高的温度。然后将第二薄层电介质材料沉积在第一薄层介电材料的正上方，然后集成电路结构再次暴露于升高的温度。进行该过程以确保包含第一和第二沉积的薄电介质层的复合层在热处理之后表现出压缩的残余应力。沉积附加的薄介电层然后将半导体晶片暴露于升高的温度的步骤可以重复进行，直到已形成足够的复合材料厚度的介电材料，通常为约至约为。

6. 发明授权

US06204192B1 Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures 有权
标题翻译：在集成电路结构中的铜金属化的至少一个低介电常数绝缘层中形成的开口的等离子体清洁工艺
公开(公告)号：US06204192B1
公开(公告)日：2001-03-20
申请号：US09281602
申请日：1999-03-29
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： H01L2100
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/7681 , H01L21/76814 , H01L21/76826
摘要： A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.
摘要翻译：提供了一种用于从集成电路结构的铜金属互连层上去除在低介电常数绝缘材料的一层或多层中形成的一个或多个开口的蚀刻残留物的工艺，其包括清洁铜互连层的表面的暴露部分在一个或多个开口的底部，该方法包括提供各向异性氢等离子体以引起等离子体中的离子与一个或多个开口底部的蚀刻残留物（包括暴露的铜表面上的氧化铜）的化学反应，从而清洁铜表面的暴露部分，并且在不溅射开口底部的铜的情况下除去蚀刻残留物。

7. 发明授权

US5994775A Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same 失效
标题翻译：金属填充通孔/接触开口，具有集成电路结构中的薄势垒层，用于快速响应，以及制造方法
公开(公告)号：US5994775A
公开(公告)日：1999-11-30
申请号：US932614
申请日：1997-09-17
申请人： Joe W. Zhao , Wilbur G. Catabay
发明人： Joe W. Zhao , Wilbur G. Catabay
IPC分类号： H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5226 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L2924/0002
摘要： The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.
摘要翻译：本发明包括集成电路结构及其制造方法，其包括介电层中的通孔/接触开口; 在通孔/接触开口的侧壁和底表面上具有至少约50埃但不超过约200埃的厚度的氮化钛的CVD层，以提供填充材料对下层和侧壁表面的附着开口在氮化钛层上形成厚度为约50埃，但不超过约300埃的钨的CVD阻挡层; 并且通孔/接触开口的其余部分填充有选自铜，CVD铝和强力填充铝的高导电性金属。

8. 发明授权

US5953631A Low stress, highly conformal CVD metal thin film 失效
标题翻译：低应力，高保形CVD金属薄膜
公开(公告)号：US5953631A
公开(公告)日：1999-09-14
申请号：US592870
申请日：1996-01-24
申请人： Joe W. Zhao , Wilbur G. Catabay
发明人： Joe W. Zhao , Wilbur G. Catabay
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76843
摘要： A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.
摘要翻译：提出了一种在衬底上沉积低应力，高保形金属薄膜（如钨）的方法。提供基板，并加热至第一温度。通过使第一组工艺气体反应，将金属薄膜的第一部分沉积在衬底上。金属薄膜的第一部分的沉积在第一时间段之后停止，并且将基板加热到大于第一温度的第二温度。金属薄膜的第二部分通过使第二组工艺气体反应而沉积在衬底上。金属薄膜的第二部分包含与金属薄膜的第一部分相同的金属。金属薄膜的第二部分的沉积在第二时间长度之后停止。还描述了具有低应力，高保形薄膜的半导体器件。

9. 发明授权

US5789028A Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride 失效
标题翻译：在氮化钛的金属有机化学气相沉积中消除半导体衬底端部剥离的方法
公开(公告)号：US5789028A
公开(公告)日：1998-08-04
申请号：US811818
申请日：1997-03-04
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： C23C16/34 , C23C16/44 , C23C16/455 , H01L21/28 , H01L21/285
CPC分类号： C23C16/45521 , C23C16/34 , C23C16/455
摘要： A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing. Such flow of deposition-inhibiting gas or gases may be directed toward the end edge of the substrate by flowing such deposition-inhibiting gas or gases through bores provided in the underlying substrate support pedestal which bores have openings peripherally spaced around the pedestal, adjacent the top of the pedestal, through which such gas or gases then exit beneath the plane of the top surface of the substrate and adjacent the end edge of the substrate.
摘要翻译：描述了一种方法和装置，用于通过MOCVD在半导体衬底的端部边缘上抑制但不完全消除氮化钛的沉积，该方法包括将一个或多个沉积抑制气体沿着方向其基本上反对处理气体朝向基板的端部边缘的流动。这种沉积抑制气体朝向衬底的端部边缘的流动减少了氮化钛在半导体衬底的端部边缘处的沉积，或者通过将一些工艺气体流从衬底的这种端部边缘引导，或者通过在邻近衬底的端边缘的沉积室的区域中或通过前述的某些组合来局部稀释这些工艺气体。这种沉积抑制气体或气体的流动可以通过使这种沉积抑制气体或气体通过设置在下面的基底支撑基座中的孔而被引向衬底的端部边缘，孔中具有围绕基座周向间隔开的开口，邻近顶部基座的这种气体或气体然后在衬底的顶表面的平面之下离开并且靠近衬底的端边缘。

10. 发明授权

US5895267A Method to obtain a low resistivity and conformity chemical vapor deposition titanium film 失效
标题翻译：获得低电阻率和一致性化学气相沉积钛膜的方法
公开(公告)号：US5895267A
公开(公告)日：1999-04-20
申请号：US889839
申请日：1997-07-09
申请人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
发明人： Joe W. Zhao , Wei-Jen Hsia , Wilbur G. Catabay
IPC分类号： C23C16/18 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843
摘要： A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.
摘要翻译：描述了通过两阶段沉积工艺形成高度保形的具有高阶梯覆盖和低电阻率的氮化钛阻挡层的方法。氮化钛阻挡层的低温沉积提供高度一致性和良好的阶梯覆盖但具有高电阻率的材料。氮化钛阻挡层的高温沉积产生低电阻率的材料。因此，通过本发明的方法在低温高温下以分离的步骤沉积的氮化钛阻挡层特别适用于特征在于窄和深接触孔的现代密度增加的装置。

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