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    • 1. 发明授权
    • Nonvolatile semiconductor memory device and write method for the same
    • 非易失性半导体存储器件和写入方法相同
    • US08254168B2
    • 2012-08-28
    • US12820342
    • 2010-06-22
    • Yuya SuzukiRieko Tanaka
    • Yuya SuzukiRieko Tanaka
    • G11C11/34
    • G11C16/26G11C11/5628G11C11/5642G11C16/0483G11C16/3459G11C2211/5621
    • According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage.
    • 根据一个实施例,半导体器件包括存储器单元,位线,写入电路和读出放大器。 位线连接到存储单元。 感测放大器被配置为将所选择的存储器单元所连接的位线偏置到第一电压,直到所选存储器单元的阈值达到第一写入状态的值。 然后,当所选择的存储单元的阈值达到第一写入状态的值时,位线被偏置到高于第一电压的第二电压。 当所选存储单元的阈值达到第二写入状态的值时,位线被连续地偏置到高于第二电压的第三电压。 连接到与所选存储单元不同的存储单元的未选择存储单元的位线被偏置到第三电压。
    • 3. 发明授权
    • Semiconductor storage device
    • 半导体存储设备
    • US08243524B2
    • 2012-08-14
    • US12723864
    • 2010-03-15
    • Yuya SuzukiToshiki HisadaYoshikazu Hosomura
    • Yuya SuzukiToshiki HisadaYoshikazu Hosomura
    • G11C16/06
    • G11C8/10G11C16/26H01L27/11519H01L27/11521H01L27/11524H01L27/11526
    • A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.
    • 半导体存储装置具有读出放大器。 读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连,并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上部互连件,并且连接到设置在所述第二上部互连件下方的所述虚拟接触互连件。
    • 5. 发明授权
    • Semiconductor storage device
    • 半导体存储设备
    • US08498139B2
    • 2013-07-30
    • US13224504
    • 2011-09-02
    • Yuya SuzukiToshiaki Edahiro
    • Yuya SuzukiToshiaki Edahiro
    • G11C5/02G11C5/06G11C16/06G11C7/10
    • G11C7/062G11C16/0483G11C16/26
    • A memory includes plurality of word lines extending in a first direction, plurality of bit lines extending in a second direction to intersect with the word lines, and a memory cell array including plurality of memory cells connected to the word lines and the bit lines. Plurality of sense amplifiers include detectors configured to detect data transmitted from the memory cells to sense nodes via the corresponding bit lines, and capacitors connected between the sense nodes and a reference potential, respectively, and are provided to be arranged in the second direction from at least a side of one ends of the bit lines. Each of k capacitors corresponding to k detectors, where k is equal to or greater than 2, has a width corresponding to widths of the k detectors, the k capacitors are arranged in the second direction, and the k detectors are arranged in the first direction.
    • 存储器包括在第一方向上延伸的多个字线,在第二方向上延伸以与字线相交的多个位线,以及包括连接到字线和位线的多个存储单元的存储单元阵列。 多个感测放大器包括检测器,其被配置为检测从存储器单元发送的数据,以经由相应位线检测节点,以及分别连接在感测节点和参考电位之间的电容器,并且被设置成沿着第二方向从 至少一端的位线的一端。 对应于k个检测器的k个电容器中的每一个k,其中k等于或大于2,具有对应于k个检测器的宽度的宽度,k个电容器被布置在第二方向上,并且k个检测器被布置在第一方向 。
    • 9. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL AND DATA WRITING METHOD THEREOF
    • 包含非易失性存储器单元的半导体存储器件及其数据写入方法
    • US20100329013A1
    • 2010-12-30
    • US12759941
    • 2010-04-14
    • Go SHIKATAYuya Suzuki
    • Go SHIKATAYuya Suzuki
    • G11C16/04
    • G11C16/0483G11C16/10G11C16/3454G11C16/3459
    • A semiconductor memory device includes memory cells, bit lines, and first and second control circuits. The first control circuit supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changes a supply state of the write control voltage to further write the data when the selected memory cell reaches a first write state by the write, the first control circuit further changes the supply state of the write control voltage to prohibit the write when the selected memory cell reaches a second write state by the write. The second control circuit controls a rising of the write control voltage when the first control circuit starts the writing to make the selected memory cell the second write state.
    • 半导体存储器件包括存储器单元,位线以及第一和第二控制电路。 第一控制电路向选择的存储单元提供写入电压和写入控制电压以将数据写入所选择的存储单元中,第一控制电路改变写入控制电压的供应状态,以在所选择的存储器 单元通过写入达到第一写入状态,则第一控制电路进一步改变写入控制电压的供应状态,以便当所选择的存储器单元通过写入达到第二写入状态时禁止写入。 当第一控制电路开始写入时,第二控制电路控制写入控制电压的上升,以使所选择的存储单元成为第二写入状态。