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    • 1. 发明授权
    • Image capturing apparatus and image processing method
    • 图像捕获装置和图像处理方法
    • US08531583B2
    • 2013-09-10
    • US12921225
    • 2009-03-10
    • Yuuichirou KimijimaHideyuki Rengakuji
    • Yuuichirou KimijimaHideyuki Rengakuji
    • H04N5/225H04N5/232
    • H04N5/23212G02B7/34G03B13/36H04N5/23216H04N5/3572
    • An image capturing apparatus comprises an image sensor comprising an imaging pixel for receiving light through an opening with a center position coincident with the optical axis of a microlens, first and second focus detection pixels for receiving pupil-divided light through a first and second opening offset in first and second directions from the optical axis of a microlens, respectively; ROM for storing shading correction data; correction coefficient generation unit for generating shading correction coefficients respectively for the imaging pixel, and the first and second focus detection pixels from the shading correction data; and correction unit for subjecting a signal for the imaging pixel to shading correction with the use of the shading correction coefficient for the imaging pixel, and subjecting signals for the first and second focus detection pixels to shading correction with the use of the shading correction coefficients for the first and second focus detection pixels.
    • 一种图像捕获装置,包括:图像传感器,包括用于通过具有与微透镜的光轴重合的中心位置的开口接收光的成像像素,用于经由第一和第二开口偏移接收光瞳分割光的第一和第二焦点检测像素 分别在微透镜的光轴的第一和第二方向上; 用于存储阴影校正数据的ROM; 校正系数生成单元,用于分别从成像像素生成阴影校正系数,以及从阴影校正数据生成第一和第二焦点检测像素; 以及校正单元,用于使用成像像素的阴影校正系数对成像像素的信号进行阴影校正,并且使用阴影校正系数对第一和第二焦点检测像素的信号进行阴影校正, 第一和第二焦点检测像素。
    • 2. 发明申请
    • IMAGE CAPTURING APPARATUS AND IMAGE PROCESSING METHOD
    • 图像捕获设备和图像处理方法
    • US20110019028A1
    • 2011-01-27
    • US12921225
    • 2009-03-10
    • Yuuichirou KimijimaHideyuki Rengakuji
    • Yuuichirou KimijimaHideyuki Rengakuji
    • H04N5/228
    • H04N5/23212G02B7/34G03B13/36H04N5/23216H04N5/3572
    • An image capturing apparatus comprises an image sensor comprising an imaging pixel for receiving light through an opening with a center position coincident with the optical axis of a microlens, first and second focus detection pixels for receiving pupil-divided light through a first and second opening offset in first and second directions from the optical axis of a microlens, respectively; ROM for storing shading correction data; correction coefficient generation unit for generating shading correction coefficients respectively for the imaging pixel, and the first and second focus detection pixels from the shading correction data; and correction unit for subjecting a signal for the imaging pixel to shading correction with the use of the shading correction coefficient for the imaging pixel, and subjecting signals for the first and second focus detection pixels to shading correction with the use of the shading correction coefficients for the first and second focus detection pixels.
    • 一种图像捕获装置,包括:图像传感器,包括用于通过具有与微透镜的光轴重合的中心位置的开口接收光的成像像素,用于经由第一和第二开口偏移接收光瞳分割光的第一和第二焦点检测像素 分别在微透镜的光轴的第一和第二方向上; 用于存储阴影校正数据的ROM; 校正系数生成单元,用于分别从成像像素生成阴影校正系数,以及从阴影校正数据生成第一和第二焦点检测像素; 以及校正单元,用于使用成像像素的阴影校正系数对成像像素的信号进行阴影校正,并且使用阴影校正系数对第一和第二焦点检测像素的信号进行阴影校正, 第一和第二焦点检测像素。
    • 8. 发明授权
    • Image signal processing apparatus, memory control method, and program for implementing the method
    • 图像信号处理装置,存储器控制方法和用于实现该方法的程序
    • US07796136B2
    • 2010-09-14
    • US11176865
    • 2005-07-07
    • Shin TakagiHideyuki Rengakuji
    • Shin TakagiHideyuki Rengakuji
    • G06F15/167G06F12/02G09G5/397
    • G09G5/39G06F3/147
    • An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit. A memory controller controls read/write operations for image signals in the respective storage areas of the VRAM section based on the management information stored in the VRAM management information section.
    • 一种图像信号处理装置,其能够防止“同时显示原始图像和紧接在前的图像”以及帧的丢弃。 信号处理器对应于从图像拾取装置输出的对象的图像拾取信号进行信号处理。 VRAM(视频随机存取存储器)部分由存储从信号处理电路输出的图像信号的至少三个存储区域组成。 VRAM管理信息部存储表示VRAM部的各个存储区域的存储状态的管理信息。 压缩电路对从VRAM部分读取的图像信号进行压缩处理。 图像显示处理电路对从VRAM部分读取的图像信号进行图像显示处理。 图像显示部分基于从图像显示处理电路输出的图像信号显示图像。 存储器控制器基于存储在VRAM管理信息部分中的管理信息来控制VRAM部分的各个存储区域中的图像信号的读/写操作。
    • 9. 发明申请
    • Register configuration control device, register configuration control method, and program for implementing the method
    • 寄存器配置控制装置,寄存器配置控制方法和实现方法的程序
    • US20060250858A1
    • 2006-11-09
    • US11429033
    • 2006-05-05
    • Saori HoudaHideyuki Rengakuji
    • Saori HoudaHideyuki Rengakuji
    • G11C7/00
    • G06F9/4411G06F3/14G09G5/02G09G5/06G09G5/393G09G5/395G09G2310/061G09G2320/0285
    • A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing. A data selector 110 selects one of the register configuration value information sent from the FIFO selector 103 and the register configuration value information output from the FIFO 108 or 109, according to a predetermined priority, and outputs the selected register configuration value information.
    • 一种电阻配置控制装置,其能够在不显示电路规模的情况下在非显示期间更新电阻配置值。 FIFO选择器103接收包括寄存器配置值和地址信息的寄存器配置值信息,并且基于地址信息从FIFO 108和109中选择要发送寄存器配置值信息的发送目的地,并发送寄存器配置 价值信息到所选择的目的地。 FIFO 108或109临时存储从FIFO选择器103发送的寄存器配置值信息,并且在预定定时读出并输出寄存器配置值信息。 数据选择器110根据预定的优先级,从FIFO选择器103发送的寄存器配置值信息和从FIFO 108或109输出的寄存器配置值信息之一选择一个,并输出所选择的寄存器配置值信息。